IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 46

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

4–12
Table 4–10. Serial Data Interface
Table 4–11. Dynamic Reconfiguration Interface
Altera Transceiver PHY IP Core User Guide
xaui_rx_serial_data[3:0]
xaui_tx_serial_data[3:0]
reconfig_togxb_data[3:0]
reconfig_fromgxb[67:0]
Transceiver Serial Data Interface
Dynamic Reconfiguration Interface
Signal Name
Signal Name
1
Table 4–10
are four lanes of serial data for both the TX and RX interfaces. This interface runs at
3.125 GHz. There is no separate clock signal because it is encoded in the data.
As silicon progresses towards smaller process nodes, circuit performance is affected
more by variations due to process, voltage, and temperature. These process variations
result in analog voltages that can be offset from required ranges. Dynamic
reconfiguration compensates for variations due to process, voltage, and temperature.
Table 4–11
core includes a single transceiver quad, these signals are internal to the core. If your
design uses more than one quad, they are external.
Dynamic reconfiguration is only supported for Stratix IV devices in the current
release.
describes the signals in the reconfiguration interface. If your XAUI PHY IP
describes the signals in the XAUI transceiver serial data interface. There
Direction
Direction
Output
Output
Input
Input
Serial input data.
Serial output data.
Reconfiguration signals from the Transceiver Reconfiguration IP
core to the XAUI transceiver.
Reconfiguration signals from the XAUI transceiver to the
Transceiver Reconfiguration IP core. For XAUI variants using a
hard PCS and PMA, reconfig_fromgxb[67:17] are terminated
to ground internally. The soft PCS in Stratix IV GX and GT devices
use 68 bits.
Description
Description
December 2010 Altera Corporation
Chapter 4: XAUI PHY IP Core
Interfaces