IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 54

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–2
Device Family Support
Performance and Resource Utilization
Parameter Settings
Table 5–3. Parameters
Altera Transceiver PHY IP Core User Guide
Device family
Parameter
f
For more detailed information about the Interlaken transceiver channel datapath,
clocking, and channel placement, refer to the “Interlaken” section in the
Protocol Configurations in Stratix V Devices
IP cores provide either final or preliminary support for target Altera device families.
These terms have the following definitions:
■
■
Table 5–1
device families
Table 5–1. Device Family Support
Table 5–2
configurations using the current version of the Quartus II software targeting a
Stratix V (5SGXMB6R2F45C2) device.
633
Table 5–2. Interlaken Performance and Resource Utilization—Stratix V Device
To configure the Interlaken IP core in the parameter editor, click Installed Plug-Ins >
Interfaces > Interlaken > Interlaken PHY v10.1. The Interlaken IP core is only
available when you select the Stratix V device family.
This section describes the Interlaken PHY parameters, which you can set using the
parameter editor.
tab.
Stratix V devices–hard PCS + hard PMA
Other device families
Stratix V
Final support—Verified with final timing models for this device.
Preliminary support—Verified with preliminary timing models for this device.
Number of Lanes
10
15
20
shows the level of support offered by the Interlaken PHY IP core for Altera
shows the typical expected device resource utilization for different
1
4
Value
Device Family
Table 5–3
Combinational ALUTs
describes the parameters that you can set on the General
Specifies the device family.
General
434
509
633
753
951
chapter of the Stratix V Device Handbook.
Preliminary
No support.
Logic Registers
Description
263
346
517
659
916
December 2010 Altera Corporation
Chapter 5: Interlaken PHY IP Core
Support
Memory Bits
Device Family Support
Transceiver
0
0
0
0
0