IPR-SDRAM/DDR Altera, IPR-SDRAM/DDR Datasheet - Page 55

• Manufacturer Part Number: IPR-SDRAM/DDR
• Description: IP CORE Renewal Of IP-SDRAM/DDR
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 3: Functional Description
Interfaces & Signals
Interfaces & Signals
Interface Description
© March 2009 Altera Corporation
f
1
For Stratix II devices, you have the following three options for the constraints:
■
■
■
This section describes the following topics:
■
■
This section describes the following local-side interface requests:
■
■
■
■
■
■
These interface requests are for the native interface. For information on the
Avalon-MM interface, refer to the
The native interface is a superset of the Avalon-MM interface. The native interface has
the following additional signals. These signals, which are not part of the Avalon-MM
interface, provide extra information and control for the native interface:
■
■
■
■
■
For information on the datapath interface, refer to
Dedicated top and bottom I/O pins, which gives the highest performance.
Migratable DM, DQ, and DQS pin constraints on all sides of the device, which
allows you to migrate your design to a migration device at a later stage, and gives
less pins.
Non-migratable pin constraints, which give much greater flexibility and a greater
number of available pins on all sides of the device.
“Interface Description” on page 3–19
“Signals” on page 3–28
“Writes” on page 3–20
“Reads” on page 3–21
“Read-Write-Read-Write” on page 3–23
“Read-Write-Read-Write” on page 3–23
“DDR SDRAM Initialization Timing” on page 3–25
“DDR2 SDRAM Initialization Timing” on page 3–26
local_rdvalid_in_n
local_init_done
local_refresh_req
local_refresh_ack
local_wdata_req
Avalon Interface
DDR and DDR2 SDRAM Controller Compiler User Guide
Specifications.
“Datapath” on page
3–4.
3–19