IPR-SDRAM/DDR Altera, IPR-SDRAM/DDR Datasheet - Page 88

• Manufacturer Part Number: IPR-SDRAM/DDR
• Description: IP CORE Renewal Of IP-SDRAM/DDR
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

A–10
Intermediate Resynchronization Registers
DQS Postamble
DDR and DDR2 SDRAM Controller Compiler User Guide
Figure A–6
registers, T1. This time T1 may not be sufficient to latch the data properly. If the
negative edge of the system clock latches data, there is time T2 to latch the
resynchronized data. To latch the data with the negative system clock edge, turn on
Insert an intermediate resynchronization register (refer to
Figure A–6. Time Between Resynchronization and System Clock
Figure A–7. Inserting an Intermediate Resynchronization Register
The DDR and DDR2 SDRAM DQ and DQS pins use the SSTL I/O standard. When
neither the FPGA nor the SDRAM device are driving the DQ and DQS pins, the
signals go to a high-impedance state. Because a pull-up resistor terminates both DQ
and DQS to V
the specification for the SSTL I/O standard, this state is an intermediate logic level
and the input buffer may interpret it as either a logic high or logic low. If there is any
noise on the DQS line, the input buffer may interpret the noise as strobe edges.
When the DQS signal transitions to a high-impedance state after a read postamble,
you must disable the DQS capture registers. This action ensures the captured data is
not corrupted before it is successfully resynchronized.
shows the time available to latch the data from the resynchronization
TT
the effective voltage on the high-impedance line is V
Resynchronization
Resynchronization
Resynchronization
System Clock
Clock
Clock
Clock
Intermediate
Register
System Clock
System Clock
T1
T2
Figure
© March 2009 Altera Corporation
A–7).
TT
. According to
DQS Postamble