IPR-SDRAM/DDR Altera, IPR-SDRAM/DDR Datasheet - Page 57
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IPR-SDRAM/DDR
Manufacturer Part Number
IPR-SDRAM/DDR
Description
IP CORE Renewal Of IP-SDRAM/DDR
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-SDRAM/DDR
Software Application
IP CORE, Memory Controllers, SDRAM
Supported Families
Cyclone, HardCopy, Stratix
Features
Data Mask Signals For Partial Write Operations, Bank Management Architecture
Core Architecture
FPGA
Core Sub-architecture
Cyclone, HardCopy, Stratix
Rohs Compliant
NA
Function
DDR SDRAM Controller
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
Chapter 3: Functional Description
Interfaces & Signals
© March 2009 Altera Corporation
1
1. The user logic requests the first write, by asserting the local_write_req signal,
2. The user logic requests a second write to a sequential address, this time of size 2 (4
3. The controller requests the write data and byte enables for the first write from the
4. The user logic requests the third write to a different chip select. The controller is
5. When it has issued the necessary bank activation command, the controller issues
6. Even though no data is being written to memory, the ddr_dqs signal must
For the Avalon-MM interface you should present the address (local_addr), the
write data (local_wdtata), and the write request (local_write_req) signal to
the controller with reference to the memory clock (clk_to_sdram). The Avalon-MM
interface does not use local_wdata_req.
Reads
Figure 3–14 on page 3–22
allows you to use any burst length up to the maximum burst length set on the
memory device. For example, if you select burst length of 8 for your DDR SDRAM
memory, the controller allows bursts of length 1, 2, 3, and 4 (2, 4, 6, and 8 on the DDR
SDRAM side).
The concept is similar for DDR2 SDRAM although only burst lengths 1 and 2 (2 and 4
on the DDR2 SDRAM side) are available.
and the size and address for this write. In this example, the request is a burst of
length 1 (2 on the DDR SDRAM side) to chip select 1. The local_ready signal is
asserted, which indicates that the controller has accepted this request, and the user
logic can request another read or write in the following clock cycle. If the
local_ready signal was not asserted, the user logic must keep the write request,
size, and address signals asserted.
on the DDR SDRAM side). The local_ready signal remains asserted, which
indicates that the controller has accepted the request.
user logic. The write data and byte enables must be presented in the clock cycle
after the request. In this example, the controller also continues to request write
data for the subsequent writes. The user logic must be able to supply the write
data for the entire burst when it requests a write.
able to buffer up to four requests so the local_ready signal stays high and the
request is accepted.
the first two write requests sequentially to the memory device.
continue toggling for the entire length of the memory device's burst length (8 in
this example).
shows three read requests of different sizes. The controller
DDR and DDR2 SDRAM Controller Compiler User Guide
3–21