IPR-SDRAM/DDR Altera, IPR-SDRAM/DDR Datasheet - Page 84

• Manufacturer Part Number: IPR-SDRAM/DDR
• Description: IP CORE Renewal Of IP-SDRAM/DDR
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

A–6
Figure A–2. Resynchronization Registers—Stratix II Devices with Fed-back Resynchronization
Notes to
(1) IP Toolbench automatically inserts the intermediate resynchronization registers, depending on your choice of resynchronization phase.
(2) IP Toolbench automatically inserts these registers if the design needs them.
DDR and DDR2 SDRAM Controller Compiler User Guide
Figure
local_rdata
Fed-back PLL
(Optional)
PLL
A–2:
resynch_clk
resynch_clk
Intermediate resynchronization registers
fedback_
Figure A–2
capture and optional fed-back clock (refer to
clk
Clocked by Fed-back Clock
Clocked by delayed DQS Clock
Clocked by Resynchronization Clock
Clocked by System Clock
(see Note 1)
Reclock resynchronized data
shows the resynchronization registers for Stratix II devices with DQS
to rising edge registers
(see Note 2)
Resynchronization registers
Table 3–15 on page
Capture registers
90
o
© March 2009 Altera Corporation
3–35).
Resynchronization
DQS
DQ