MFRC52302HN1,151 NXP Semiconductors, MFRC52302HN1,151 Datasheet - Page 16

• Manufacturer Part Number: MFRC52302HN1,151
• Description: IC READER 32-HVQFN
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC52302HN1,151

• Rf Type: Read / Write
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935293911151

NXP Semiconductors
MFRC523
Product data sheet
COMPANY PUBLIC
8.3.4 I
The address byte must meet the following formats:
Table 15.
An I
serial bus interface to the host. The I
NXP Semiconductors’ I
interface can only act in slave mode. Therefore the MFRC523 does not perform clock
generation or access arbitration.
The MFRC523 can act as a slave receiver or slave transmitter in Standard mode, Fast
mode and High-speed mode.
SDA is a bidirectional line connected to a positive supply voltage using a current source or
a pull-up resistor. Both SDA and SCL lines are set HIGH when data is not transmitted. The
MFRC523 has a 3-state output stage to perform the wired-AND function. Data on the
I
400 kBd in Fast mode or up to 3.4 Mbit/s in High-speed mode.
If the I
as defined in the I
See
Bit 7
(MSB)
1 or 0
2
2
Fig 11. I
•
•
•
C-bus can be transferred at data rates of up to 100 kBd in Standard mode, up to
C Bus Interface
2
the MSB of the first byte sets the mode used
– the MSB is set to logic 0 to write data to the MFRC523
– the MSB is set to logic 1 to read data from the MFRC523
bit 6 is reserved for future use
bits [5:0] define the address; see
Table 156 on page 77
C-bus interface is supported and enables implementation of a low-cost, low pin count
2
C-bus interface is selected, spike suppression is activated on lines SCL and SDA
2
Address byte 0 register; address MOSI
C-bus interface
Bit 6
reserved
All information provided in this document is subject to legal disclaimers.
MICROCONTROLLER
2
C-bus interface specification.
Rev. 3.7 — 8 November 2011
Bit 5
address
2
C-bus interface specification, rev. 2.1, January 2000. The
for timing requirements.
115237
Bit 4
address
NETWORK
2
PULL-UP
Table 15
C-bus interface is implemented based on
CONFIGURATION
WIRING
Bit 3
address
NETWORK
PULL-UP
Bit 2
address
SDA
SCL
I2C
EA
ADR_[5:0]
MFRC523
Contactless reader IC
address
Bit 1
001aal160
MFRC523
© NXP B.V. 2011. All rights reserved.
Bit 0
(LSB)
address
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