MFRC52302HN1,151 NXP Semiconductors, MFRC52302HN1,151 Datasheet - Page 93

• Manufacturer Part Number: MFRC52302HN1,151
• Description: IC READER 32-HVQFN
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC52302HN1,151

• Rf Type: Read / Write
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935293911151

NXP Semiconductors
26. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. BR_T0 and BR_T1 settings . . . . . . . . . . . . . . .12
Table 11. Selectable UART transfer speeds . . . . . . . . . .13
Table 12. UART framing . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 13. Read data byte order . . . . . . . . . . . . . . . . . . . .14
Table 14. Write data byte order . . . . . . . . . . . . . . . . . . . .14
Table 15. Address byte 0 register; address MOSI . . . . . .16
Table 16. Register and bit settings controlling the signal on
Table 17. Register and bit settings controlling the signal on
Table 18. CRC coprocessor parameters . . . . . . . . . . . . .27
Table 19. Interrupt sources . . . . . . . . . . . . . . . . . . . . . . .29
Table 20. Behavior of register bits and their designation .32
Table 21. MFRC523 register overview . . . . . . . . . . . . . .33
Table 22. Reserved register (address 00h); reset value: 00h
Table 23. Reserved register bit descriptions . . . . . . . . . .36
Table 24. CommandReg register (address 01h); reset
Table 25. CommandReg register bit descriptions . . . . . .36
Table 26. ComIEnReg register (address 02h); reset value:
Table 27. ComIEnReg register bit descriptions . . . . . . . .37
Table 28. DivIEnReg register (address 03h); reset value:
Table 29. DivIEnReg register bit descriptions . . . . . . . . .37
Table 30. ComIrqReg register (address 04h); reset value:
Table 31. ComIrqReg register bit descriptions . . . . . . . .38
Table 32. DivIrqReg register (address 05h); reset value: x0h
Table 33. DivIrqReg register bit descriptions . . . . . . . . . .39
Table 34. ErrorReg register (address 06h); reset value: 00h
Table 35. ErrorReg register bit descriptions . . . . . . . . . .40
Table 36. Status1Reg register (address 07h); reset value:
MFRC523
Product data sheet
COMPANY PUBLIC
Quick reference data . . . . . . . . . . . . . . . . . . . . .2
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .6
Communication overview for ISO/IEC 14443 A
reader/writer . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Connection protocol for detecting different
interface types . . . . . . . . . . . . . . . . . . . . . . . . .10
MOSI and MISO byte order . . . . . . . . . . . . . . . 11
MOSI and MISO byte order . . . . . . . . . . . . . . . 11
SPI read address . . . . . . . . . . . . . . . . . . . . . . . 11
SPI write address . . . . . . . . . . . . . . . . . . . . . .12
pin TX1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
pin TX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .36
value: 20h bit allocation . . . . . . . . . . . . . . . . . .36
80h bit allocation . . . . . . . . . . . . . . . . . . . . . . .37
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . .37
14h bit allocation . . . . . . . . . . . . . . . . . . . . . . .38
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .39
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .40
21h bit allocation . . . . . . . . . . . . . . . . . . . . . . .40
All information provided in this document is subject to legal disclaimers.
Rev. 3.7 — 8 November 2011
115237
Table 37. Status1Reg register bit descriptions . . . . . . . . 41
Table 38. Status2Reg register (address 08h); reset value:
Table 39. Status2Reg register bit descriptions . . . . . . . . 41
Table 40. FIFODataReg register (address 09h); reset value:
Table 41. FIFODataReg register bit descriptions . . . . . . 42
Table 42. FIFOLevelReg register (address 0Ah); reset
Table 43. FIFOLevelReg register bit descriptions . . . . . . 43
Table 44. WaterLevelReg register (address 0Bh); reset
Table 45. WaterLevelReg register bit descriptions . . . . . 43
Table 46. ControlReg register (address 0Ch); reset value:
Table 47. ControlReg register bit descriptions . . . . . . . . 43
Table 48. BitFramingReg register (address 0Dh); reset
Table 49. BitFramingReg register bit descriptions . . . . . 44
Table 50. CollReg register (address 0Eh); reset value: xxh
Table 51. CollReg register bit descriptions . . . . . . . . . . . 44
Table 52. Reserved register (address 0Fh); reset value: 00h
Table 53. Reserved register bit descriptions . . . . . . . . . . 45
Table 54. Reserved register (address 10h); reset value: 00h
Table 55. Reserved register bit descriptions . . . . . . . . . . 45
Table 56. ModeReg register (address 11h); reset value: 3Fh
Table 57. ModeReg register bit descriptions . . . . . . . . . 46
Table 58. TxModeReg register (address 12h); reset value:
Table 59. TxModeReg register bit descriptions . . . . . . . 47
Table 60. RxModeReg register (address 13h); reset value:
Table 61. RxModeReg register bit descriptions . . . . . . . 47
Table 62. TxControlReg register (address 14h); reset value:
Table 63. TxControlReg register bit descriptions . . . . . . 48
Table 64. TxASKReg register (address 15h); reset value:
Table 65. TxASKReg register bit descriptions . . . . . . . . 49
Table 66. TxSelReg register (address 16h); reset value: 10h
Table 67. TxSelReg register bit descriptions . . . . . . . . . 49
Table 68. RxSelReg register (address 17h); reset value: 84h
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 41
xxh bit allocation . . . . . . . . . . . . . . . . . . . . . . . 42
value: 00h bit allocation . . . . . . . . . . . . . . . . . 42
value: 08h bit allocation . . . . . . . . . . . . . . . . . 43
10h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 43
value: 00h bit allocation . . . . . . . . . . . . . . . . . 44
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 44
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 45
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 45
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 46
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 47
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 47
80h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 48
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 49
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 49
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Contactless reader IC
MFRC523
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