MFRC52302HN1,151 NXP Semiconductors, MFRC52302HN1,151 Datasheet - Page 46
MFRC52302HN1,151
Manufacturer Part Number
MFRC52302HN1,151
Description
IC READER 32-HVQFN
Manufacturer
NXP Semiconductors
Series
MIFARE®r
Datasheet
1.MFRC52302HN1151.pdf
(98 pages)
Specifications of MFRC52302HN1,151
Rf Type
Read / Write
Frequency
13.56MHz
Features
ISO14443-A, ISO14443-B
Package / Case
32-VFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
935293911151
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NXP Semiconductors
MFRC523
Product data sheet
COMPANY PUBLIC
9.2.2.2 ModeReg register
Defines general mode settings for transmitting and receiving.
Table 56.
Table 57.
Bit
Symbol
Access
Bit
7
6
5
4
3
2
1 to 0
Symbol
MSBFirst
reserved
TxWaitRF
reserved
PolMFin
reserved
CRCPreset
[1:0]
MSBFirst reserved TxWaitRF reserved
ModeReg register (address 11h); reset value: 3Fh bit allocation
ModeReg register bit descriptions
R/W
7
All information provided in this document is subject to legal disclaimers.
Rev. 3.7 — 8 November 2011
Value
1
-
1
-
1
0
-
00
01
10
11
6
-
Description
CRC coprocessor calculates the CRC with MSB first. In the
CRCResultReg register the values for the CRCResultMSB[7:0]
bits and the CRCResultLSB[7:0] bits are bit reversed
Remark: during RF communication this bit is ignored
reserved for future use
transmitter can only be started if an RF field is generated
reserved for future use
defines the polarity of pin MFIN
Remark: the internal envelope signal is encoded active LOW,
changing this bit generates a MFinActIRq event
reserved for future use
defines the preset value for the CRC coprocessor for the CalcCRC
command
Remark: during any communication, the preset values are
selected automatically according to the definition of bits in the
RxModeReg and TxModeReg registers
115237
polarity of pin MFIN is active HIGH
polarity of pin MFIN is active LOW
0000h
6363h
A671h
FFFFh
R/W
5
4
-
PolMFin
R/W
3
reserved
2
-
Contactless reader IC
MFRC523
© NXP B.V. 2011. All rights reserved.
CRCPreset[1:0]
1
R/W
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