MFRC52302HN1,151 NXP Semiconductors, MFRC52302HN1,151 Datasheet - Page 48

• Manufacturer Part Number: MFRC52302HN1,151
• Description: IC READER 32-HVQFN
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC52302HN1,151

• Rf Type: Read / Write
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935293911151

NXP Semiconductors
MFRC523
Product data sheet
COMPANY PUBLIC
9.2.2.5 TxControlReg register
Table 61.
Controls the logical behavior of the antenna driver pins TX1 and TX2.
Table 62.
Table 63.
Bit
6 to 4
3
2
1 to 0
Bit
Symbol InvTx2RF
Access
Bit Symbol
7
6
5
4
InvTx2RFOn 1
InvTx1RFOn 1
InvTx2RFOff 1
InvTx1RFOff 1
Symbol
RxSpeed[2:0]
RxNoErr
RxMultiple
RxFraming
RxModeReg register bit descriptions
TxControlReg register (address 14h); reset value: 80h bit allocation
TxControlReg register bit descriptions
R/W
On
7
All information provided in this document is subject to legal disclaimers.
Value Description
InvTx1RF
Rev. 3.7 — 8 November 2011
R/W
On
1
Value
000
001
010
011
100
101
110
111
0
1
00
01
10
11
6
output signal on pin TX2 inverted when driver TX2 is enabled
output signal on pin TX1 inverted when driver TX1 is enabled
output signal on pin TX2 inverted when driver TX2 is disabled
output signal on pin TX1 inverted when driver TX1 is disabled
InvTx2RF
115237
Description
defines the bit rate while receiving data. The MFRC523
manages transfer speeds up to 848 kBd
an invalid received data stream (less than 4 bits received) will
be ignored and the receiver remains active
receiver is deactivated after receiving a data frame
able to receive more than one data frame
only valid for data rates above 106 kBd in order to handle the
polling command
after setting this bit, the Receive and Transceive commands will
not terminate automatically. Multiple reception can only be
deactivated by writing any command (except the Receive
command) to the CommandReg register, or by the host clearing
the bit
if set to logic 1, an error byte is added to the FIFO buffer at the
end of a received data stream which is a copy of the ErrorReg
register value
defines the expected framing for data reception
R/W
106 kBd
212 kBd
424 kBd
848 kBd
reserved
reserved
reserved
reserved
ISO/IEC 14443 A/MIFARE
reserved
reserved
ISO/IEC 14443 B
Off
5
InvTx1RF
R/W
Off
4
…continued
Tx2CW reserved Tx2RFEn Tx1RFEn
R/W
3
2
-
Contactless reader IC
MFRC523
© NXP B.V. 2011. All rights reserved.
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