XR21V1410IL-0C-EB Exar Corporation, XR21V1410IL-0C-EB Datasheet - Page 23

• Manufacturer Part Number: XR21V1410IL-0C-EB
• Description: Interface Modules & Development Tools For XR21V1410 QFN16 USB, RS485;No Cables
• Manufacturer: Exar Corporation
• Series: -r

Specifications of XR21V1410IL-0C-EB

• Interface Type: RS-232, USB
• Operating Supply Voltage: 3.3 V
• Product: Interface Modules
• Silicon Core Number: XR21V1410
• Application Sub Type: UART
• Kit Contents: Board
• Main Purpose: Interface, USB 2.0 to UART
• Embedded: No
• Utilized Ic / Part: XR21V1410IL
• Primary Attributes: -
• Secondary Attributes: -
• Silicon Manufacturer: Exar
• Kit Application Type: Communication & Networking
• For Use With/related Products: XR21V1410
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.2.0
This register enables the Wide mode functionality for the UART.
WIDE_MODE[0]: Enable wide mode
WIDE_MODE[7:1]: Reserved
These bits are reserved and should remain ’0’.
This register is automatically set to logic ’1’ for baud rates below 46921 bps, and can be manually set for baud
rates of 46921 bps and higher. This register enables the Low latency feature of the UART. Write to this
register following any desired baud rate setting change.
LOW_LATENCY[0]: Enable Low Latency mode
LOW_LATENCY[7:1]: Reserved
These bits are reserved and should remain ’0’.
This register is used to enable / disable GPIO status in the high data byte of the custom interrupt packet. See
Table 16, “Interrupt Packet Format,” on page 24 and Table 18, “Data Field of Customized Interrupt Packet -
Exar Vendor Specific,” on page 25.
CUSTOM_INT_PACKET[0]: GPIO1
CUSTOM_INT_PACKET[1]: GPIO2
CUSTOM_INT_PACKET[2]: Reserved
CUSTOM_INT_PACKET[3]: GPIO0
CUSTOM_INT_PACKET[4]: GPIO3
CUSTOM_INT_PACKET[5]: GPIO4
3.4.1
3.4.2
3.4.3
Logic 0 = Normal (7, 8 or 9 bit data) mode
Logic 1 = Wide mode -
Wide mode Receive” on page
Logic 0 = Receive data is not forwarded from the Rx FIFO until bMaxPacketSize (64 bytes) or timeout (3
characters) has occurred.
Logic 1 = All data in the RX FIFO is provided to the USB host at the next BULK IN request irrespective of the
number of bytes in the FIFO.
Logic 0 = Disable GPIO1 status in custom interrupt packet.
Logic 1 = Enable GPIO1 status in custom interrupt packet.
Logic 0 = Disable GPIO2 status in custom interrupt packet.
Logic 1 = Enable GPIO2 status in custom interrupt packet.
This bit is reserved and should remain ’0’.
Logic 0 = Disable GPIO0 status in custom interrupt packet.
Logic 1 = Enable GPIO0 status in custom interrupt packet.
Logic 0 = Disable GPIO3 status in custom interrupt packet.
Logic 1 = Enable GPIO3 status in custom interrupt packet.
WIDE_MODE Register Description (Read/Write)
LOW_LATENCY Register Description (Read/Write)
CUSTOM_INT_PACKET (Read/Write)
See
“Section 1.5.1.1, Wide Mode Transmit” on page 7
7.
23
1-CH FULL-SPEED USB UART
and
“Section 1.5.2.1,
XR21V1410