P0071 Terasic Technologies Inc, P0071 Datasheet - Page 60
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P0071
Manufacturer Part Number
P0071
Description
TPAD MULTIMEDIADEVELOPMENT KIT
Manufacturer
Terasic Technologies Inc
Series
tPAD, Cyclone®IVr
Specifications of P0071
Main Purpose
Reference Design, Tablet
Embedded
Yes, FPGA / CPLD
Utilized Ic / Part
EP4CE115
Primary Attributes
8-Inch TFT LCD, LED Backlight
Secondary Attributes
5-Megapixel Digital Image Sensor
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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The DE2-115 board is equipped with an Analog Device ADV7180 TV decoder chip. The ADV7180
is an integrated video decoder that automatically detects and converts a standard analog baseband
television signals (NTSC, PAL, and SECAM) into 4:2:2 component video data compatible with the
8-bit ITU-R BT.656 interface standard. The ADV7180 is compatible with a broad range of video
devices, including DVD players, tape-based sources, broadcast sources, and security/surveillance
cameras.
The registers in the TV decoder can be programmed by a serial I2C bus, which is connected to the
Cyclone IV E FPGA as indicated in
(U6) is 0x40/0x41. The pin assignments are listed in
ADV7180 is available on the manufacturer‟s website, or in the DE2_115_datasheets\TV Decoder
folder on the DE2-115 System CD.
ENET1_TX_CLK
ENET1_TX_DATA[0]
ENET1_TX_DATA[1]
ENET1_TX_DATA[2]
ENET1_TX_DATA[3]
ENET1_TX_EN
ENET1_TX_ER
ENETCLK_25
4
.
.
1
1
5
5
T
T
V
V
D
D
e
e
c
c
o
o
Figure 4-29 Connections between FPGA and TV Decoder
d
d
PIN_C22
PIN_C25
PIN_A26
PIN_B26
PIN_C26
PIN_B25
PIN_A25
PIN_A14
e
e
r
r
Figure
MII transmit clock 2
MII transmit data[0] 2
MII transmit data[1] 2
MII transmit data[2] 2
MII transmit data[3] 2
GMII and MII transmit enable 2
GMII and MII transmit error 2
Ethernet clock source
4-29. Note that the I2C address W/R of the TV decoder
59
Table
4-24. Detailed information of the
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
3.3V
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