LFE2-50E-L-EV Lattice, LFE2-50E-L-EV Datasheet - Page 11

• Manufacturer Part Number: LFE2-50E-L-EV
• Description: MCU, MPU & DSP Development Tools ECP-2 Standard Eval Board
• Manufacturer: Lattice

Specifications of LFE2-50E-L-EV

• Processor To Be Evaluated: LatticeECP2
• Interface Type: RS-232, Ethernet
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 26. sysIO Standards Supported per Bank
PCI/PCI-X
The LatticeECP2 Standard Evaluation Board is designed to be compatible with PCI (PCI SIG 2.2 specification) and
PCI-X (Mode 1). All necessary signals required for 64-bit PCI/PCI-X operation are provided, as shown in Table 27
and Table 28.
Table 27. PCI Connections - Solder Side
Types of I/O Buffers
Output Standards
Supported
Inputs
Clock Inputs
PCI Support
LVDS Output Buffers
1. These differential standards are implemented by using complementary LVCMOS drivers and external resistors.
2. Available on 50% of the I/Os in the Bank.
Description
J48
1
2
3
4
5
6
7
Single-ended
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18 Class I, II
SSTL25 Class I, II
SSTL33 Class I, II
HSTL15 Class I
HSTL18_I, II
SSTL18D Class I, II
SSTL25D Class I, II
SSTL33D Class I, II
HSTL15D Class I
HSTL18D Class I, II
PCI33
LVDS25E
LVPECL
BLVDS
RSDS
All Single-ended, Differ-
ential
All Single-ended, Differ-
ential
PCI33 no clamp
PCI_TRSTN
+12V
PCI_TMS
PCI_TDI
+5V
PCI_INTA_N
PCI_INTC_N
Signal Name
1
Banks 0-1
Top Side,
1
1
1
Single-ended and
Differential
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18 Class I, II
SSTL25 Class I, II
SSTL33 Class I, II
HSTL15 Class I
HSTL18 Class I, II
SSTL18D Class I, II
SSTL25D Class I, II
SSTL33D Class I, II
HSTL15D Class I, II
HSTL18D Class I, II
PCI33
LVDS
LVDS25E
LVPECL
BLVDS
RSDS
All Single-ended,
Differential
All Single-ended,
Differential
PCI33 no clamp
LVDS (3.5mA) Buffers
LatticeECP2 Pin
Right Side,
1
Banks 2-3
1
1
1
11
-
-
-
-
-
-
-
LatticeECP2 Standard Evaluation Board
2
Single-ended
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18 Class I
SSTL2 Class I, II
SSTL3 Class I, II
HSTL15 Class I
HSTL18 Class I, II
SSTL18D Class I, II
SSTL25D Class I, II,
SSTL33D Class I, II
HSTL15D Class I
HSTL18D Class I, II
PCI33
LVDS25E
LVPECL
BLVDS
RSDS
All Single-ended,
Differential
All Single-ended,
Differential
PCI33 with clamp
Bottom Side,
sysIO Bank
1
Banks 4-5
1
1
1
-
-
-
-
-
-
-
Single-ended and
Differential
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18 Class I
SSTL2 Class I, II
SSTL3 Class I, II
HSTL15 Class I, III
HSTL18 Class I, II, III
SSTL18D Class I,
SSTL25D Class I, II,
SSTL33D_I, II
HSTL15D Class I
HSTL18D Class I, II
PCI33
LVDS
LVDS25E
LVPECL
BLVDS
RSDS
All Single-ended,
Differential
All Single-ended,
Differential
PCI33 no clamp
LVDS (3.5mA) Buffers
TP10, PD if master
Decoupling cap
TP11, PU if master
TP12, J14-4, J13
NC
J19
J19
User’s Guide
1
Banks 6-7
Left Side,
1
1
1
Note
2