LFE2-50E-L-EV Lattice, LFE2-50E-L-EV Datasheet - Page 9

• Manufacturer Part Number: LFE2-50E-L-EV
• Description: MCU, MPU & DSP Development Tools ECP-2 Standard Eval Board
• Manufacturer: Lattice

Specifications of LFE2-50E-L-EV

• Processor To Be Evaluated: LatticeECP2
• Interface Type: RS-232, Ethernet
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 20. Jumper Settings for SPI Emulation via J40
Power Setup
For stand-alone board operation, i.e. outside of a PCI/PCI-X backplane, the evaluation board must be supplied with
a single 5V DC power supply. 5V DC power may be applied using an AC adapter, such as the Condor Electronics
S-5V0-4A0-U11-206IP (or similar), plugged into the power jack at J47, or via the banana jacks at J45 (ground) and
J46 (5V DC).
Table 21. AC Adaptor Specifications
When the board is inserted into a PCI/PCI-X backplane, the on-board 3.3V regulator is automatically disabled; all
onboard power will be derived from the PCI/PCI-X 3.3V power rail.
Additional on-board regulators supply 1.2V, an adjustable voltage, and 5V (for the optional LCD panel). The adjust-
able voltage is set by the potentiometer R36, on the right side of the board, and can be set to any value between
1.22V and 2.5V.
The header at J30 allows a current measuring device to be inserted between 1.2V and the FPGA core. To measure
current remove power from the board, remove all of the jumpers at J30, install a meter between the odd pins and
the even pins, for example between pins 1 and 2, and apply power to the board. When measurement is complete,
remove power from the board and re-install all three jumpers.
Table 22. 1.2V to V
The header at J29 allows a current measuring device to be inserted between 3.3V and the FPGA’s V
measure current, remove power from the board, remove the jumper at J29, install a meter between pins 1 and 2,
and apply power to the board. When measurement is complete, remove power from the board and re-install the
jumper.
Location
J30
CC
Position
1 to 2
3 to 4
5 to 6
Core
Location
J35, J36
J35, J36
J31
J32
J33
J34
J43
J44
Connects 1.2V to the FPGA Core
Voltage
Current Capacity
Polarity
Connector I.D.
Connector O.D.
Position
2 to 3
1 to 2
1 to 2
3 to 4
5 to 6
1 to 2
Open
Open
Open
Open
9
5VDC +/- 10%
Up to 4A
Positive Center
0.1” (2.5mm)
0.218” (5.5mm)
Function
Open if driven by cable
Open if driven by cable
Open if driven by cable
Bypass Overflow
Not allowed
LatticeECP2 Standard Evaluation Board
Notes
User’s Guide
Default
CCAUX.
X
X
X
To