LFE2-50E-L-EV Lattice, LFE2-50E-L-EV Datasheet - Page 4

• Manufacturer Part Number: LFE2-50E-L-EV
• Description: MCU, MPU & DSP Development Tools ECP-2 Standard Eval Board
• Manufacturer: Lattice

Specifications of LFE2-50E-L-EV

• Processor To Be Evaluated: LatticeECP2
• Interface Type: RS-232, Ethernet
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
The 8-pin device footprint is at U4; the 16-pin device footprint is at U5. Only one location can be populated at a
time.
Configuration/Programming Headers
Two programming headers are provided on the evaluation board, providing access to the LatticeECP2 JTAG port
and sysCONFIG™ port. The JTAG connector is a 1x10 header and the sysCONFIG connector is a 2x17 header.
Both the JTAG and the sysCONFIG ports are also provided with loop-through connectors to allow for easy daisy
chaining of multiple boards. With proper jumper selection (see the next section) standard IDC ribbon cable can be
used without the need to swap wires on the cable.
See the Configuring/Programming The Board section of this document for more information on this topic.
The pinouts for these headers are provided in the following tables.
Note: A parallel port ispDOWNLOAD
using a parallel port (1x8) ispDOWNLOAD cable, connect pin 1 of the cable to pin 1 of the 1x10 JTAG header. For
more information on the ispDOWNLOAD Cable, see the ispDOWNLOAD Cables Data Sheet available on the Lat-
tice web site at www.latticesemi.com.
Table 1. JTAG Programming Header Pinout
Table 2. JTAG Loop-Through Header Pinout
®
Vcc (3.3V)
TDO
TDI
PROGN
N/C
TMS
Ground
TCK
DONE
INIT Chain
1. See section below on jumpers.
N/C
TDO Chain
TDI Chain
PROGN
N/C
TMS
Ground
TCK
DONE
INIT Chain
1. See section below on jumpers.
cable is included with each LatticeECP2 Standard Evaluation Board. When
1
1
1
Function
Function
1
1
1
1
1
1
4
LatticeECP2 Standard Evaluation Board
J4 (1x10)
J5 (1x10)
10
10
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
User’s Guide