LFE2-50E-L-EV Lattice, LFE2-50E-L-EV Datasheet - Page 3

• Manufacturer Part Number: LFE2-50E-L-EV
• Description: MCU, MPU & DSP Development Tools ECP-2 Standard Eval Board
• Manufacturer: Lattice

Specifications of LFE2-50E-L-EV

• Processor To Be Evaluated: LatticeECP2
• Interface Type: RS-232, Ethernet
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
• Humidity: < 95% without condensation
• 5VDC input (+/- 10%) up to 4A, or 3.3V input from PCI/PCI-X backplane
Additional Resources
Additional resources relating to the LatticeECP2 Standard Evaluation Board (including updated documentation,
and sample programs) can be found at the following URL:
www.latticesemi.com/products/developmenthardware/fpgafspcboards/ecp2stardevaluationboard.cfm
Features
LatticeECP2 Device
This board features a LatticeECP2 FPGA with a 1.2V DC core in a 484-ball fpBGA package. A complete descrip-
tion of this device can be found in the LatticeECP2 Family Data Sheet available on the Lattice web site at www.lat-
ticesemi.com/ecp2.
On-Board Oscillator
The 3.3V oscillator socket at Y1 accepts both full-size (14-pin) and half-size (8-pin) oscillators, and will route the
oscillator output to a LatticeECP2 primary clock input or a PLL input, depending on the oscillator’s position in the
socket (see Figure 2).
When a full size oscillator is installed such that pin 1 of the oscillator aligns with pin 1 of the socket, the output of
the oscillator drives the primary clock at LatticeECP2 pin J21 (this is the default position). When pin 1 of the oscilla-
tor is aligned to pin 2 of the socket, the clock is routed to LatticeECP2 pin J21. When using a half size oscillator,
align pin 1 of the oscillator to pin 1 of the socket to drive the primary clock, or align pin 1 of the oscillator to pin 5 of
the socket to drive the PLL. Note that pin 1 of the oscillator is expected to be a no-connect pin.
Figure 2. Oscillator Options
SPI Serial Flash
SPI Serial Flash are available in three package styles, two of those packages, 8-pin SO and 16-pin SO, are sup-
ported by this board. In general, the 8-pin devices support densities up to 16Mb, while the 16-pin devices support
larger densities. The device chosen for inclusion on this board depends on the density of the installed LatticeECP2,
but the SPI Serial Flash will be large enough to allow two bitstreams to be stored simultaneously in order to support
SPIm mode.
GND
GND
Default
Position
Pin-1
Pin-1
Pin-16
Pin-16
3.3V
Primary Clock
(J21)
PLL Clock
(N21)
3.3V
Primary Clock
(J21)
PLL Clock
(N21)
3
GND
GND
LatticeECP2 Standard Evaluation Board
Pin-1
Pin-1
Pin-16
Pin-16
User’s Guide
3.3V
Primary Clock
(J21)
PLL Clock
(N21)
3.3V
Primary Clock
(J21)
PLL Clock
(N21)