C8051F206DK-G Silicon Laboratories Inc, C8051F206DK-G Datasheet - Page 113
C8051F206DK-G
Manufacturer Part Number
C8051F206DK-G
Description
MCU, MPU & DSP Development Tools MCU DEVELOPMENT KIT W/ GLOBAL POWER SPLY
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F226DK.pdf
(146 pages)
Specifications of C8051F206DK-G
Processor To Be Evaluated
C8051F206
Data Bus Width
8 bit
Interface Type
USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Multiple masters may reside on the same bus. A Mode Fault flag (MODF, SPI0CN.5) is set to logic 1 when
the SPI is configured as a master (MSTEN = 1) and its slave select signal NSS is pulled low. When the
Mode Fault flag is set, the MSTEN and SPIEN bits of the SPI control register are cleared by hardware,
thereby placing the SPI module in an "off-line" state. In a multiple-master environment, the system control-
ler should check the state of the SLVSEL flag (SPI0CN.2) to ensure the bus is free before setting the
MSTEN bit and initiating a data transfer.
15.2. Serial Clock Timing
As shown in Figure 15.4, four combinations of serial clock phase and polarity can be selected using the
clock control bits in the SPI Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.7) selects one
of two clock phases (edge used to latch the data). The CKPOL bit (SPI0CFG.6) selects between an active-
high or active-low clock. Both master and slave devices must be configured to use the same clock phase
and polarity. Note: the SPI should be disabled (by clearing the SPIEN bit, SPI0CN.0) while changing the
clock phase and polarity.
The SPI Clock Rate Register (SPI0CKR) as shown in SFR Definition 15.3 controls the master mode serial
clock frequency. This register is ignored when operating in slave mode.
15.3. SPI Special Function Registers
The SPI is accessed and controlled through four special function registers in the system controller:
SPI0CN Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock
Rate Register. The four special function registers related to the operation of the SPI Bus are described in
the following section.
(CK POL = 0,CK PHA = 0)
(CK POL = 0,CK PHA =1)
(CK POL =1, CK PHA =0)
(CK POL =1, CK PHA =1)
SCK
SCK
SCK
SCK
MISO/MOSI
NSS
MSB
Figure 15.4. Full Duplex Operation
Bit 6
Bit 5
Rev. 1.6
Bit 4
Bit 3
Bit 2
Bit 1
C8051F2xx
LSB
113
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