C8051F206DK-G Silicon Laboratories Inc, C8051F206DK-G Datasheet - Page 134

• Manufacturer Part Number: C8051F206DK-G
• Description: MCU, MPU & DSP Development Tools MCU DEVELOPMENT KIT W/ GLOBAL POWER SPLY
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F206DK-G

• Processor To Be Evaluated: C8051F206
• Data Bus Width: 8 bit
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

C8051F2xx
17.2.1. Mode 0: 16-bit Counter/Timer with Capture
In this mode, Timer 2 operates as a 16-bit counter/timer with capture facility. A high-to-low transition on the
T2EX input pin causes the 16-bit value in Timer 2 (TH2, TL2) to be loaded into the capture registers
(RCAP2H, RCAP2L).
Timer 2 can use either SYSCLK, SYSCLK divided by 12, or high-to-low transitions on the external T2 input
pin as its clock source when operating in Counter/Timer with Capture mode. Clearing the C/T2 bit
(T2CON.1) selects the system clock as the input for the timer (divided by one or twelve as specified by the
Timer Clock Select bit T2M in CKCON). When C/T2 is set to logic 1, a high-to-low transition at the T2 input
pin increments the counter/timer register. As the 16-bit counter/timer register increments and overflows
from 0xFFFF to 0x0000, the TF2 timer overflow flag (T2CON.7) is set and an interrupt will occur if the inter-
rupt is enabled.
Counter/Timer with Capture mode is selected by setting the Capture/Reload Select bit CP/RL2 (T2CON.0)
and the Timer 2 Run Control bit TR2 (T2CON.2) to logic 1. The Timer 2 External Enable EXEN2
(T2CON.3) must also be set to logic 1 to enable a capture. If EXEN2 is cleared, transitions on T2EX will
be ignored.
134
SYSCLK
T2EX
T2
PORT0
PORT0
MUX
MUX
EXEN2
12
TR2
0
1
Figure 17.4. T2 Mode 0 Block Diagram
0
1
CKCON
M
T
2
Capture
Rev. 1.6
M
T
1
TCLK
M
T
0
RCAP2L
TL2
RCAP2H
TH2
CP/RL2
EXEN2
RCLK
TCLK
EXF2
C/T2
TR2
TF2
Interrupt