C8051F206DK-G Silicon Laboratories Inc, C8051F206DK-G Datasheet - Page 114

• Manufacturer Part Number: C8051F206DK-G
• Description: MCU, MPU & DSP Development Tools MCU DEVELOPMENT KIT W/ GLOBAL POWER SPLY
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F206DK-G

• Processor To Be Evaluated: C8051F206
• Data Bus Width: 8 bit
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

C8051F2xx
114
Bit7:
Bit6:
Bits5–3: BC2–BC0: SPI Bit Count.
Bits2–0:
CKPHA
R/W
Bit7
CKPHA: SPI Clock Phase.
This bit controls the SPI clock phase.
0: Data sampled on first edge of SCK period.
1: Data sampled on second edge of SCK period.
CKPOL: SPI Clock Polarity.
This bit controls the SPI clock polarity. 
0: SCK line low in idle state.
1: SCK line high in idle state.
Indicates which of the up to 8 bits of the SPI word have been transmitted.
These three bits determine the number of bits to shift in/out of the SPI shift register during a
data transfer in master mode. They are ignored in slave mode.
SPIFRS2–SPIFRS0: SPI Frame Size. 
0
0
0
0
1
1
1
1
CKPOL
0
0
0
0
1
1
1
1
R/W
Bit6
BC2 – BC0
SPIFRS
SFR Definition 15.1. SPI0CFG: SPI Configuration
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
BC2
Bit5
R
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
BC1
Bit4
R
Bit Transmitted
Bits Shifted
Bit 7 (MSB)
Bit 0 (LSB)
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
1
2
3
4
5
6
7
8
Rev. 1.6
BC0
Bit3
R
SPIFRS2 SPIFRS1 SPIFRS0
R/W
Bit2
R/W
Bit1
R/W
Bit0
SFR Address:
Reset Value
00000111
0x9A