MEDIA5200KIT1 Freescale Semiconductor, MEDIA5200KIT1 Datasheet - Page 15

MCU, MPU & DSP Development Tools MEDIA5200 SW DEVT SYSTEM

MEDIA5200KIT1

Manufacturer Part Number
MEDIA5200KIT1
Description
MCU, MPU & DSP Development Tools MEDIA5200 SW DEVT SYSTEM
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MEDIA5200KIT1

Processor To Be Evaluated
MPC5200B
Data Bus Width
32 bit
Interface Type
Ethernet, USB
Lead Free Status / Rohs Status
Not Compliant
For additional information, see the MPC5200B User’s Manual (MPC5200BUM).
1.3.4.1
During reset (HRESET and PORRESET) the Reset Configuration Word is latched in the related Reset Configuration Word
Register with each rising edge of the SYS_XTAL signal. If both resets (HRESET and PORRESET) are inactive (high), the
contents of this register are locked immediately with the SYS_XTAL clock (see
1.3.5
The MPC5200B provides three different kinds of external interrupts:
The propagation of these three kinds of interrupts to the core is shown in the following graphic:
Freescale Semiconductor
Four IRQ interrupts
Eight GPIO interrupts with simple interrupt capability (not available in power-down mode)
Eight WakeUp interrupts (special GPIO pins)
RST_CFG_WRD
External Interrupts
Reset Configuration Word
PORRESET
Beware of changing the values on the pins of the reset configuration word after the
deassertion of PORRESET. This may cause problems because it may change the internal
clock ratios and so extend the PLL locking process.
SYS_XTAL
HRESET
sample
sample
Figure 3. Reset Configuration Word Locking
sample
sample
MPC5200B Data Sheet, Rev. 4
sample sample
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NOTE
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4096 clocks
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Figure
sample
3).
LOCK
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