MEDIA5200KIT1 Freescale Semiconductor, MEDIA5200KIT1 Datasheet - Page 29

• Manufacturer Part Number: MEDIA5200KIT1
• Description: MCU, MPU & DSP Development Tools MEDIA5200 SW DEVT SYSTEM
• Manufacturer: Freescale Semiconductor

Specifications of MEDIA5200KIT1

• Processor To Be Evaluated: MPC5200B
• Data Bus Width: 32 bit
• Interface Type: Ethernet, USB
• Lead Free Status / Rohs Status: Not Compliant

All ATA transfers are programmed in terms of system clock cycles (IP bus clocks) in the ATA Host Controller timing registers.
This puts constraints on the ATA protocols and their respective timing modes in which the ATA Controller can communicate
with the drive.
Faster ATA modes (i.e., UDMA 0, 1, 2) are supported when the system is running at a sufficient frequency to provide adequate
data transfer rates. Adequate data transfer rates are a function of the following:
The ATA clock is the same frequency as the IP bus clock in MPC5200B. See the MPC5200B User’s Manual (MPC5200B).
Freescale Semiconductor
•
•
•
Sym
t
t
t
t
t
t
t
t
t
t
t
2i
A
B
0
1
2
3
4
5
6
9
The MPC5200B operating frequency (IP bus clock frequency)
Internal MPC5200B bus latencies
Other system load dependent variables
Address valid to DIOR/DIOW setup
DIOR/DIOW pulse width 16-bit
DIOR/DIOW recovery time
PIO Timing Parameter
DIOR/DIOW to address
All output timing numbers are specified for nominal 50 pF loads.
IORDY pulse width
DIOW data setup
DIOR data setup
DIOW data hold
DIOR data hold
IORDY setup
Cycle Time
valid hold
8-bit
Table 27. PIO Mode Timing Specifications
MPC5200B Data Sheet, Rev. 4
Min/Max
(ns)
max
max
min
min
min
min
min
min
min
min
min
min
NOTE
Mode 0
1250
(ns)
600
165
290
70
60
30
50
20
35
—
5
Mode 1
1250
(ns)
383
125
290
50
45
20
35
15
35
—
5
Mode 2
1250
(ns)
240
100
290
30
30
15
20
10
35
—
5
Mode 3
1250
(ns)
180
30
80
80
70
30
10
20
10
35
5
Mode 4
1250
(ns)
120
25
70
70
25
20
10
20
10
35
5
SpecID
A8.10
A8.11
A8.1
A8.2
A8.3
A8.4
A8.5
A8.6
A8.7
A8.8
A8.9
29