MEDIA5200KIT1 Freescale Semiconductor, MEDIA5200KIT1 Datasheet - Page 39

MCU, MPU & DSP Development Tools MEDIA5200 SW DEVT SYSTEM

MEDIA5200KIT1

Manufacturer Part Number
MEDIA5200KIT1
Description
MCU, MPU & DSP Development Tools MEDIA5200 SW DEVT SYSTEM
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MEDIA5200KIT1

Processor To Be Evaluated
MPC5200B
Data Bus Width
32 bit
Interface Type
Ethernet, USB
Lead Free Status / Rohs Status
Not Compliant
Freescale Semiconductor
1
Sym
The TX_CLK frequency shall be 25% of the nominal transmit frequency, e.g., a PHY operating at 100 Mb/s must provide
a TX_CLK frequency of 25 MHz and a PHY operating at 10 Mb/s must provide a TX_CLK frequency of 2.5 MHz. See
the IEEE 802.3 Specification.
t
t
t
t
Sym
5
6
7
8
t
9
TX_CLK rising edge to TXD[3:0], TX_EN, TX_ER valid
TX_CLK rising edge to TXD[3:0], TX_EN, TX_ER
TXD[3:0] (Outputs)
CRS, COL minimum pulse width
TX_CLK (Input)
TX_CLK pulse width high
TX_CLK pulse width low
Figure 28. Ethernet Timing Diagram—MII Tx Signal
Description
Figure 29. Ethernet Timing Diagram—MII Async
TX_EN
TX_ER
Description
invalid
CRS, COL
Table 33. MII Async Signal Timing
Table 32. MII Tx Signal Timing
MPC5200B Data Sheet, Rev. 4
t
t
6
5
t
7
t
9
t
8
35%
35%
Min
5
Min
1.5
65%
65%
Max
25
Max
TX_CLK Period
TX_CLK Period
TX_CLK Period
Unit
Unit
ns
ns
(1)
(1)
SpecID
A9.9
SpecID
A9.5
A9.6
A9.7
A9.8
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