AD7887AR-REEL7 Analog Devices Inc, AD7887AR-REEL7 Datasheet - Page 11

• Manufacturer Part Number: AD7887AR-REEL7
• Description: IC,Data Acquisition System,2-CHANNEL,12-BIT,SOP,8PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD7887AR-REEL7

• Rohs Status: RoHS non-compliant
• Design Resources: Software Calibrated, 1 MHz to 8 GHz, 70 dB RF Power Measurement System Using AD8318 (CN0150)
• Number Of Bits: 12
• Sampling Rate (per Second): 125k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 3.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)

THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7887 is a fast, low power, 12-bit, single-supply, single-
channel/dual-channel ADC. The part can be operated from a
3 V (2.7 V to 3.6 V) supply or from a 5 V (4.75 V to 5.25 V) supply.
When operated from either a 5 V or 3 V supply, the AD7887 is
capable of throughput rates of 125 kSPS when provided with a
2 MHz clock.
The AD7887 provides the user with an on-chip, track/hold
analog-to-digital converter reference and a serial interface
housed in an 8-lead package. The serial clock input accesses data
from the part and provides the clock source for the successive
approximation ADC. The part can be configured for single-
channel or dual-channel operation. When configured as a
single-channel part, the analog input range is 0 to V
externally applied V
the AD7887 is configured for two input channels, the input
range is determined by internal connections to be 0 to V
If single-channel operation is required, the AD7887 can be
operated in a read-only mode by tying the DIN line permanently
to GND. For applications where the user wants to change the
mode of operation or wants to operate the AD7887 as a dual-
channel ADC, the DIN line can be used to clock data into the
part’s control register.
CONVERTER OPERATION
The AD7887 is a successive approximation ADC built around a
charge-redistribution DAC. Figure 8 and Figure 9 show simplified
schematics of the ADC. Figure 8 shows the ADC during its
acquisition phase. SW2 is closed and SW1 is in Position A, the
comparator is held in a balanced condition, and the sampling
capacitor acquires the signal on AIN.
When the ADC starts a conversion (see Figure 9), SW2 opens
and SW1 moves to Position B, causing the comparator to become
unbalanced. The control logic and the charge-redistribution DAC
are used to add and subtract fixed amounts of charge from the
sampling capacitor to bring the comparator back into a balanced
condition. When the comparator is rebalanced, the conversion
is complete. The control logic generates the ADC output code.
Figure 10 shows the ADC transfer function.
AIN
AGND
A
SW1
(REF IN/REF OUT)/2
B
CAPACITOR
SAMPLING
ACQUISITION
PHASE
Figure 8. ADC Acquisition Phase
REF
can be between 1.2 V and V
SW2
COMPARATOR
REDISTRIBUTION
REF
CONTROL
CHARGE
DD
(where the
LOGIC
DAC
). When
DD
.
Rev. D | Page 11 of 24
ADC TRANSFER FUNCTION
The output coding of the AD7887 is straight binary. The
designed code transitions occur at successive integer LSB values
(that is, 1 LSB, 2 LSB, and so on). The LSB size is V
ideal transfer characteristic for the AD7887 is shown in Figure 10.
TYPICAL CONNECTION DIAGRAM
Figure 11 shows a typical connection diagram for the AD7887.
The GND pin is connected to the analog ground plane of the
system. The part is in dual-channel mode so V
connected to a well-decoupled V
input range of 0 V to V
16-bit word with four leading zeros followed by the MSB of the
12-bit result. For applications where power consumption is of
concern, the automatic power-down at the end of conversion
should be used to improve power performance. See the Modes
of Operation section.
SUPPLY 2.7V
V
IN
TO 5.25V
AGND
0V TO V
A
SW1
(REF IN/REF OUT)/2
000 ... 010
000 ... 001
000 ... 000
111 ... 111
111 ... 110
111 ... 000
011 ... 111
INPUT
DD
B
CAPACITOR
SAMPLING
CONVERSION
0V
10µF
Figure 11. Typical Connection Diagram
PHASE
0.5LSB
Figure 10. Transfer Characteristic
Figure 9. ADC Conversion Phase
DD
0.1µF
GND
. The conversion result is output in a
AIN1
AIN2
AD7887
SW2
ANALOG INPUT
V
DD
DD
1LSB = V
DOUT
SCLK
COMPARATOR
pin to provide an analog
DIN
CS
REF
SERIAL
INTERFACE
+V
/4096
REF
REF
REDISTRIBUTION
– 1.5LSB
is internally
CONTROL
CHARGE
REF
AD7887
LOGIC
DAC
/4096. The
µC/µP