AD7887AR-REEL7 Analog Devices Inc, AD7887AR-REEL7 Datasheet - Page 18

• Manufacturer Part Number: AD7887AR-REEL7
• Description: IC,Data Acquisition System,2-CHANNEL,12-BIT,SOP,8PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD7887AR-REEL7

• Rohs Status: RoHS non-compliant
• Design Resources: Software Calibrated, 1 MHz to 8 GHz, 70 dB RF Power Measurement System Using AD8318 (CN0150)
• Number Of Bits: 12
• Sampling Rate (per Second): 125k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 3.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)

AD7887
MICROPROCESSOR INTERFACING
The serial interface on the AD7887 allows the part to be directly
connected to a range of many different microprocessors. This
section explains how to interface the AD7887 with some of the
more common microcontroller and DSP serial interface
protocols.
AD7887 to TMS320C5x
The serial interface on the TMS320C5x uses a continuous serial
clock and frame synchronization signals to synchronize the data
transfer operations with peripheral devices like the AD7887.
The CS input allows easy interfacing with an inverter between
the serial clock of the TMS320C5x and the AD7887 being the
only glue logic required. The serial port of the TMS320C5x is
set up to operate in burst mode with internal CLKX (Tx serial
clock) and FSX (Tx frame sync). The serial port control register
(SPC) must have the following setup: FO = 0, FSM = 1,
MCM = 1, and TXM = 1. The connection diagram is shown in
Figure 22
AD7887 to ADSP-21xx
The ADSP-21xx family of DSPs are easily interfaced to the
AD7887 with an inverter between the serial clock of the ADSP-
21xx and the AD7887. This is the only glue logic required. The
SPORT control register should be set up as follows:
Table 7. SPORT0 Control Register Setup
Setting
TFSW = RFSW = 1
INVRFS = INVTFS = 1
DTYPE = 00
SLEN = 1111
ISCLK = 1
TFSR = RFSR = 1
IRFS = 0
ITFS = 1
The connection diagram is shown in Figure 23. The ADSP-21xx
has the TFS and RFS of the SPORT tied together, with TFS set
as an output and RFS set as an input. The DSP operates in
alternate framing mode, and the SPORT control register is set
up as described in Table 7. The frame synchronization signal
generated on the TFS is tied to CS and, as with all signal
processing applications, equidistant sampling is necessary. In
1
ADDITIONAL PINS OMITTED FOR CLARITY.
AD7887
.
1
SCLK
DOUT
DIN
Figure 22. Interfacing to the TMS320C5x
CS
Description
Alternative framing
Active low frame signal
Right justify data
16-bit data-word
Internal serial clock
Frame every word
CLKR
DR
FSX
CLKX
DT
FSR
TMS320C5x
1
Rev. D | Page 18 of 24
this example however, the timer interrupt is used to control the
sampling rate of the ADC and, under certain conditions,
equidistant sampling cannot be achieved.
The timer registers are loaded with a value that will provide an
interrupt at the required sample interval. When an interrupt is
received, a value is transmitted with TFS/DT (ADC control
word). The TFS is used to control the RFS and hence the
reading of data. The frequency of the serial clock is set in the
SCLKDIV register. When the instruction to transmit with TFS
is given (that is, AX0 = TX0), the state of the SCLK is checked.
The DSP waits until the SCLK has gone high, low, and high
again before a transmission starts. If the timer and SCLK values
are chosen such that the instruction to transmit occurs on or
near the rising edge of SCLK, the data may be transmitted or it
may wait until the next clock edge.
For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3, a
SCLK of 2 MHz is obtained and eight master clock periods will
elapse for every one SCLK period. If the timer registers are
loaded with the value 803, 100.5 SCLKs will occur between
interrupts and subsequently between transmit instructions. This
situation results in nonequidistant sampling because the
transmit instruction is occurring on an SCLK edge. If the
number of SCLKs between interrupts is a whole integer number
of N, equidistant sampling will be implemented by the DSP.
AD7887 to DSP56xxx
The connection diagram in Figure 24 shows how the AD7887
can be connected to the SSI (synchronous serial interface) of
the DSP56xxx family of DSPs from Motorola. The SSI is
operated in synchronous mode (SYN bit in CRB = 1) with an
internally generated 1-bit clock period frame sync for both Tx
and Rx (Bits FSL1 = 1 and FSL0 = 0 in CRB). Set the word
length to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA. An
inverter is also necessary between the SCLK from the DSP56xxx
and the SCLK pin of the AD7887, as shown in Figure 24.
1
1
ADDITIONAL PINS OMITTED FOR CLARITY.
ADDITIONAL PINS OMITTED FOR CLARITY.
AD7887
AD7887
1
1
DOUT
DOUT
SCLK
SCLK
DIN
DIN
CS
CS
Figure 23. Interfacing to the ADSP-21xx
Figure 24. Interfacing to the DSP56xxx
SCLK
DR
DT
RFS
TFS
SRD
STD
SCK
SC2
ADSP-21xx
DSP56xxx
1
1