AD7887AR-REEL7 Analog Devices Inc, AD7887AR-REEL7 Datasheet - Page 5

• Manufacturer Part Number: AD7887AR-REEL7
• Description: IC,Data Acquisition System,2-CHANNEL,12-BIT,SOP,8PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD7887AR-REEL7

• Rohs Status: RoHS non-compliant
• Design Resources: Software Calibrated, 1 MHz to 8 GHz, 70 dB RF Power Measurement System Using AD8318 (CN0150)
• Number Of Bits: 12
• Sampling Rate (per Second): 125k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 3.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)

TIMING SPECIFICATIONS
Table 2.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
SCLK
CONVERT
ACQ
1
2
3
4
5
6
7
8
9
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
Mark/space ratio for the SCLK input is 40/60 to 60/40.
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
t
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
time of the part and is independent of the bus loading.
3
3
4
8
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
2
4.75 V to 5.25 V
2
14.5 × t
1.5 × t
10
30
75
20
20
0.4 × t
0.4 × t
80
5
SCLK
SCLK
SCLK
SCLK
1
Limit at T
(A, B Versions)
Figure 2. Load Circuit for Digital Output Timing Specifications
MIN
2.7 V to 3.6 V
2
14.5 × t
1.5 × t
10
60
100
20
20
0.4 × t
0.4 × t
80
5
, T
MAX
OUTPUT
SCLK
SCLK
SCLK
PIN
SCLK
TO
50pF
C
Rev. D | Page 5 of 24
L
200µA
200µA
ns max
ns max
ns max
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
μs typ
I
I
OL
OH
1.6V
8
, quoted in the timing characteristics is the true bus relinquish
Description
Throughput time = t
CS to SCLK setup time
Delay from CS until DOUT three-state disabled
Data access time after SCLK falling edge
Data setup time prior to SCLK rising edge
Data valid to SCLK hold time
SCLK high pulse width
SCLK low pulse width
CS rising edge to DOUT high impedance
Power-up time from shutdown
DD
) and timed from a voltage level of 1.6 V.
CONVERT
+ t
ACQ
= 16 t
SCLK
AD7887