AD9272BSVZRL-40 Analog Devices Inc, AD9272BSVZRL-40 Datasheet
AD9272BSVZRL-40
Specifications of AD9272BSVZRL-40
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AD9272BSVZRL-40 Summary of contents
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FEATURES 8 channels of LNA, VGA, AAF, and ADC Low noise preamplifier (LNA) Input-referred noise voltage = 0.75 nV/√Hz (gain = 21.3 dB MHz typical SPI-programmable gain = 15.6 dB/17.9 dB/21.3 dB Single-ended input; V maximum = 733 ...
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AD9272 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Product Highlights ........................................................................... 3 Specifications ..................................................................................... 4 AC Specifications .......................................................................... 4 Digital Specifications ................................................................... 8 Switching Specifications ...
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The AD9272 requires a LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data ...
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AD9272 SPECIFICATIONS AC SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, f PGA gain = 27 dB, GAIN− = 0.8 V, AAF LPF cutoff = f unless otherwise noted. Table ...
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Parameter Conditions Group Delay MHz to Variation 18 MHz, GAIN 1.6 V Input-Referred LNA gain = Noise Voltage 15.6 dB/ 17.9 dB/ 21.3 dB ∞ FB Noise Figure LNA gain ...
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AD9272 1 Parameter Conditions GAIN ACCURACY 25°C Gain Law Confor < GAIN+ < mance Error 0.16 V 0.16 V < GAIN+ < 1.44 V 1.44 V < GAIN+ < 1.6 V Linear Gain Error GAIN+ = 0.8 V, ...
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Parameter Conditions I Full-channel AVDD1 mode CW Doppler mode with four channels enabled I Full-channel mode AVDD2 CW Doppler mode with four channels enabled I DRVDD Total Power Includes output Dissipation drivers, full- channel mode, no signal CW Doppler ...
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AD9272 DIGITAL SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, f Table 2. 1 Parameter CLOCK INPUTS (CLK+, CLK−) Logic Compliance 2 Differential Input Voltage Input Common-Mode Voltage Input Resistance ...
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SWITCHING SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, f Table 3. 1 Parameter 2 CLOCK Clock Rate Clock Pulse Width High ( Clock Pulse Width Low (t ...
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AD9272 ADC Timing Diagrams N – 1 AIN t EH CLK– CLK+ t CPD DCO– DCO+ t FCO FCO– FCO DOUTx– DOUTx+ N – 1 AIN t EH CLK– CLK+ t CPD DCO– DCO+ t FCO FCO– FCO+ ...
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ABSOLUTE MAXIMUM RATINGS Table 4. With Parameter Respect To Electrical AVDD1 GND AVDD2 GND DRVDD GND GND GND AVDD2 AVDD1 AVDD1 DRVDD AVDD2 DRVDD Digital Outputs GND (DOUTx+, DOUTx−, DCO+, DCO−, FCO+, FCO−) CLK+, CLK−, GND GAIN+,GAIN− LI-x, LO-x, LOSW-x ...
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AD9272 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 LI-E 1 INDICATOR LG-E 2 AVDD2 3 AVDD1 4 LO-F 5 LOSW-F 6 LI-F 7 LG-F 8 AVDD2 9 AVDD1 10 LO-G 11 LOSW-G 12 LI-G 13 LG-G 14 AVDD2 15 AVDD1 ...
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Pin No. Name 20 LG-H 23 CLK− 24 CLK+ 27 DOUTH− 28 DOUTH+ 29 DOUTG− 30 DOUTG+ 31 DOUTF− 32 DOUTF+ 33 DOUTE− 34 DOUTE+ 35 DCO− 36 DCO+ 37 FCO− 38 FCO+ 39 DOUTD− 40 DOUTD+ 41 DOUTC− 42 ...
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AD9272 Pin No. Name 88 GAIN+ 89 RBIAS 90 VREF 91 CWD4− 92 CWD4+ 93 CWD5− 94 CWD5+ 95 CWD6− 96 CWD6+ 97 CWD7− 98 CWD7+ 99 LO-E 100 LOSW-E Description Gain Control Voltage Input True External Resistor to Set ...
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TYPICAL PERFORMANCE CHARACTERISTICS MSPS MHz Ω, LNA gain = 21.3 dB, LNA bias = high, PGA gain = 27 dB, AAF LPF cutoff = f SAMPLE IN S cutoff/20.7 (default), unless ...
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AD9272 500k 450k 400k 350k 300k 250k 200k 150k 100k 50k 0 –7 –6 –5 –4 –3 –2 – CODES Figure 11. Output-Referred Noise Histogram, GAIN 180k 160k 140k 120k 100k 80k 60k 40k 20k ...
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GAIN+ = 1.6V 75 GAIN+ = 0.8V GAIN FREQUENCY (MHz) Figure 17. Antialiasing Filter (AAF) Group Delay Response 0 –10 –20 –30 –40 GAIN+ = 0.4V ...
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AD9272 5.00MHz, = 5.01MHz IN1 IN2 FUND2 LEVEL = FUND1 LEVEL – 20dB –20 –40 –60 GAIN –80 –100 GAIN+ = 0.8V –120 –40 –35 –30 –25 –20 –15 FUND1 LEVEL (dBFS) Figure 23. ...
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EQUIVALENT CIRCUITS V AVDDx CM 15kΩ LI-x, LG-x Figure 24. Equivalent LNA Input Circuit 10Ω LO-x, LOSW-x Figure 25. Equivalent LNA Output Circuit 10Ω CLK+ 10kΩ 10kΩ 10Ω CLK– Figure 26. Equivalent Clock Input Circuit AVDDx 1.25V Rev ...
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AD9272 100Ω RBIAS Figure 30. Equivalent RBIAS Circuit AVDDx 70kΩ 1kΩ CSB Figure 31. Equivalent CSB Input Circuit VREF 6kΩ Figure 32. Equivalent VREF Circuit AVDDx Rev Page AVDD2 50Ω GAIN+ Figure 33. Equivalent GAIN+ ...
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THEORY OF OPERATION ULTRASOUND The primary application for the AD9272 is medical ultrasound. Figure 36 shows a simplified block diagram of an ultrasound system. A critical function of an ultrasound system is the time gain control (TGC) compensation for physiological ...
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AD9272 R FB1 FB2 T/R SWITCH CHANNEL OVERVIEW Each channel contains both a TGC signal path and a CW Doppler signal path. Common to both signal paths, the LNA provides user- ...
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Active Impedance Matching The LNA consists of a single-ended voltage gain amplifier with differential outputs, and the negative output is externally available. For example, with a fixed gain of 8× (17.9 dB), an active input termination is synthesized by connecting ...
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AD9272 LNA Noise The short-circuit noise voltage (input-referred noise impor- tant limit on system performance. The short-circuit input-referred noise voltage for the LNA is 0.85 nV/√ gain of 21.3 dB, including the VGA noise at a ...
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INPUT OVERDRIVE Excellent overload behavior is of primary importance in ultrasound. Both the LNA and VGA have built-in overdrive protection and quickly recover after an overload event. Input Overload Protection As with any amplifier, voltage clamping prior to the inputs ...
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AD9272 AD9272 g LNA m g LNA m SWITCH ARRAY 8 × CHANNEL g LNA m g LNA m AD9272 g LNA m g LNA m SWITCH ARRAY 8 × CHANNEL g LNA m g LNA m Figure 44. Typical ...
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Crosspoint Switch Each LNA is followed by a transconductance amp for voltage- to-current conversion. Currents can be routed to one of eight pairs of differential outputs single-ended outputs for summing. Each CWD output pin sinks 2.4 mA ...
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AD9272 Table 9. Sensitivity and Dynamic Range of Trade-Offs LNA Gain Input-Referred Full-Scale Input Noise Voltage (V p-p) (nV/√Hz) (V/V) (dB) 6 15.6 0.733 0.98 8 17.9 0.550 0.86 12 21.3 0.367 0.75 1 LNA: output full scale = 4.4 ...
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PGA GAIN = 21dB 0.3 PGA GAIN = 24dB PGA GAIN = 27dB 0.2 PGA GAIN = 30dB 0 0.2 0.4 0.6 0.8 GAIN+ (V) Figure 48. LNA with 17.9 dB Gain Setting/VGA Full-Scale Limitations ...
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AD9272 499Ω AD9272 ±0.4DC AT 100Ω 0.8V CM GAIN+ 0.01µF 0.8V CM AD8138 100Ω GAIN– ±0.4DC AT 0.01µF 0.8V CM 499Ω Figure 52. Differential GAIN± Pins Configuration VGA Noise In a typical application, a VGA compresses a wide dynamic range ...
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ADC The AD9272 uses a pipelined ADC architecture. The quantized output from each stage is combined into a 12-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample and ...
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AD9272 The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge result, any changes to the sampling frequency require approximately eight clock cycles to allow the DLL to acquire and lock to the new ...
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By asserting the PDWN pin high, the AD9272 is placed into power-down mode. In this state, the device typically dissipates 2 mW. During power-down, the LVDS output drivers are placed into a high impedance state. The AD9272 returns to normal ...
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AD9272 600 EYE: ALL BITS 400 200 100 0 –100 –200 –400 –600 –1.5ns –1.0ns –0.5ns 0ns –200ps –100ps 0ps Figure 64. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths of ...
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EYE: ALL BITS 400 200 0 –200 –400 –600 –1.5ns –1.0ns –0.5ns 0ns 0.5ns –200ps –100ps 0ps Figure 66. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω Termination On and ...
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AD9272 When using the serial port interface (SPI), the DCO± phase can be adjusted in 60° increments relative to the data edge. This enables the user to refine system timing margins if required. The default DCO± timing, as shown in ...
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Power and Ground Recommendations When connecting power to the AD9272 recommended that two separate 1.8 V supplies be used: one for analog (AVDD) and one for digital (DRVDD). If only one 1.8 V supply is available, it should ...
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AD9272 SERIAL PORT INTERFACE (SPI) The AD9272 serial port interface allows the user to configure the signal chain for specific functions or operations through a structured register space provided inside the chip. This offers the user added flexibility and customization, ...
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NUMBER OF SDIO PINS CONNECTED TOGETHER Figure 68. SDIO Pin Loading ...
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AD9272 MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map table has eight address locations. The memory map is roughly divided into three sections: the chip configuration register map (Address 0x00 to Address 0x02), the device ...
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Table 17. AD9272 Memory Map Register Addr. Bit 7 (Hex) Register Name (MSB) Bit 6 Chip Configuration Registers 00 Chip_port_config 0 LSB first off (default) 01 Chip_id 02 Chip_grade X X Device Index and Transfer ...
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AD9272 Addr. Bit 7 (Hex) Register Name (MSB) Bit 6 0F Flex_channel_input Filter cutoff frequency control 0000 = 1.3 × 1/3 × f 0001 = 1.2 × 1/3 × f 0010 = 1.1 × 1/3 × f 0011 = 1.0 ...
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Addr. Bit 7 (Hex) Register Name (MSB) Bit 6 19 User_patt1_lsb User_patt1_msb B15 B14 1B User_patt2_lsb User_patt2_msb B15 B14 21 Serial_control LSB first off (default) 22 Serial_ch_stat X ...
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... AD9272BSVZRL-65 −40°C to +85°C 1 AD9272BSVZ-40 −40°C to +85°C 1 AD9272BSVZRL-40 −40°C to +85°C 1 AD9272-65EBZ 1 AD9272-80KITZ RoHS Compliant Part. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...