AD9272BSVZRL-40 Analog Devices Inc, AD9272BSVZRL-40 Datasheet - Page 28

• Manufacturer Part Number: AD9272BSVZRL-40
• Description: 12Bit 40 MSPS Octal ADC
• Manufacturer: Analog Devices Inc
• Type: Ultrasound Receiversr

Specifications of AD9272BSVZRL-40

• Design Resources: Powering AD9272 with ADP5020 Switching Regulator PMU for Increased Efficiency (CN0135)
• Resolution (bits): 12 b
• Sampling Rate (per Second): 40M
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 1.8V, 3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9272-65EBZ - BOARD EVAL AD9272
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9272
Table 9. Sensitivity and Dynamic Range of Trade-Offs
(V/V)
6
8
12
1
2
3
4
5
6
Table 9 demonstrates the sensitivity and dynamic range of
trade-offs that can be achieved relative to various LNA and
VGA gain settings.
For example, when the VGA is set for the minimum gain voltage,
the TGC path is dominated by VGA noise and achieves the
maximum output SNR. However, as the postamp gain options
are increased, the input-referred noise is reduced, and the SNR
is degraded.
If the VGA is set for the maximum gain voltage, the TGC path
is dominated by LNA noise and achieves the lowest input-
referred noise but with degraded output SNR. The higher the
TGC (LNA + VGC) gain, the lower the output SNR. As the
postamp gain is increased, the input-referred noise is reduced.
At low gains, the VGA should limit the system noise perfor-
mance (SNR); at high gains, the noise is defined by the source and
the LNA. The maximum voltage swing is bound by the full-
scale peak-to-peak ADC input voltage (2 V p-p).
Both the LNA and VGA have full-scale limitations within each
section of the TGC path. These limitations are dependent on the
gain setting of each function block and on the voltage applied to the
LNA: output full scale = 4.4 V p-p differential.
Filter: loss ~ 1 dB, NBW = 13.3 MHz, GAIN− = 0.8 V.
ADC: 40 MSPS, 70 dB SNR, 2 V p-p full-scale input.
Channel noise at maximum VGA gain.
Output dynamic range at minimum VGA gain (VGA dominated).
Output dynamic range at maximum VGA gain (LNA dominated).
Gain
(dB)
15.6
17.9
21.3
Full-Scale Input
(V p-p)
0.733
0.550
0.367
LNA
Input-Referred
Noise Voltage
(nV/√Hz)
0.98
0.86
0.75
VGA
Postamp Gain (dB)
21
24
27
30
21
24
27
30
21
24
27
30
1, 2, 3
Rev. C | Page 28 of 44
GAIN± pins. The LNA has three limitations, or full-scale settings,
that can be applied through the SPI. Similarly, the VGA has four
postamp gain settings that can be applied through the SPI. The
voltage applied to the GAIN± pins determines which amplifier
(the LNA or VGA) saturates first. The maximum signal input level
that can be applied as a function of voltage on the GAIN± pins
for the selectable gain options of the SPI is shown in Figure 47 to
Figure 49.
GAIN+ = 0 V
67.5
66.4
64.6
62.5
67.5
66.4
64.5
62.5
67.5
66.4
64.6
62.5
Typical Output Dynamic Range
Figure 47. LNA with 15.6 dB Gain Setting/VGA Full-Scale Limitations
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
PGA GAIN = 27dB
5
0.2
PGA GAIN = 30dB
GAIN+ = 1.6 V
65.1
63.0
60.6
57.9
64.5
62.3
59.8
57.1
63.3
60.9
58.2
55.4
0.4
0.6
Channel
GAIN+ (V)
0.8
6
PGA GAIN = 21dB
PGA GAIN = 24dB
Input-Referred Noise
GAIN+ = 1.6 V (nV/√Hz)
1.395
1.286
1.227
1.197
1.149
1.071
1.030
1.009
0.910
0.865
0.842
0.830
1.0
1.2
1.4
1.6
4
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