AD9272BSVZRL-40 Analog Devices Inc, AD9272BSVZRL-40 Datasheet - Page 41

• Manufacturer Part Number: AD9272BSVZRL-40
• Description: 12Bit 40 MSPS Octal ADC
• Manufacturer: Analog Devices Inc
• Type: Ultrasound Receiversr

Specifications of AD9272BSVZRL-40

• Design Resources: Powering AD9272 with ADP5020 Switching Regulator PMU for Increased Efficiency (CN0135)
• Resolution (bits): 12 b
• Sampling Rate (per Second): 40M
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 1.8V, 3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9272-65EBZ - BOARD EVAL AD9272
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 17. AD9272 Memory Map Register
Addr.
(Hex)
Chip Configuration Registers
00
01
02
Device Index and Transfer Registers
04
05
FF
ADC Functions
08
09
0D
Register Name
Chip_port_config
Chip_id
Chip_grade
Device_index_2
Device_index_1
device_update
Modes
Clock
Test_io
0
X
X
X
User test mode
00 = off (default)
01 = on, single
alternate
10 = on, single once
11 = on, alternate once
Bit 7
(MSB)
X
X
X
Bit 6
LSB first
1 = on
0 = off
(default)
X
X
X
X
X
X
Bit 5
Soft
reset
1 = on
0 = off
(default)
Child ID[5:4]
(identify device
variants of Chip ID)
00 = 40 MSPS
(default)
01 = 65 MSPS
10 = 80 MSPS
X
Clock
Channel
DCO±
1 = on
0 = off
(default)
X
X
X
Reset PN
long
gen
1 = on
0 = off
(default)
(AD9272 = 0x2E, default)
Rev. C | Page 41 of 44
Bit 4
1
X
Clock
Channel
FCO±
1 = on
0 = off
(default)
X
X
X
Reset PN
short
gen
1 = on
0 = off
(default)
Chip ID Bits[7:0]
Bit 3
1
X
Data
Channel
H
1 = on
(default)
0 = off
Data
Channel
D
1 = on
(default)
0 = off
X
0
X
Output test mode—see Table 12
0000 = off (default)
0001 = midscale short
0010 = +FS short
0011 = −FS short
0100 = checkerboard output
0101 = PN sequence long
0110 = PN sequence short
0111 = one-/zero-word toggle
1000 = user input
1001 = 1-/0-bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency (format
determined by the output_mode register)
Bit 2
Soft
reset
1 = on
0 = off
(default)
X
Data
Channel
G
1 = on
(default)
0 = off
Data
Channel
C
1 = on
(default)
0 = off
Internal power-down mode
000 = chip run (default)
001 = full power-down
010 = standby
011 = reset
100 = CW mode (TGC PDWN)
X
X
Bit 1
LSB first
1 = on
0 = off
(default)
X
Data
Channel
F
1 = on
(default)
0 = off
Data
Channel
B
1 = on
(default)
0 = off
X
X
Bit 0
(LSB)
0
X
Data
Channel
E
1 = on
(default)
0 = off
Data
Channel
A
1 = on
(default)
0 = off
SW
transfer
1 = on
0 = off
(default)
Duty
cycle
stabilizer
1 = on
(default)
0 = off
Default
Value
0x18
Read
only
0x00
0x0F
0x0F
0x00
0x00
0x01
0x00
Default Notes/
Comments
The nibbles
should be
mirrored so that
LSB- or MSB-first
mode is set cor-
rectly regardless of
shift mode.
Default is unique
chip ID, different
for each device.
This is a read-only
register.
Child ID used to
differentiate
graded devices.
Bits are set to
determine which
on-chip device
receives the next
write command.
Bits are set to
determine which
on-chip device
receives the next
write command.
Synchronously
transfers data
from the master
shift register to
the slave.
Determines
various generic
modes of chip
operation
(global).
Turns the internal
duty cycle stabilizer
on and off
(global).
When this register
is set, the test data
is placed on the
output pins in
place of normal
data. (Local, expect
for PN sequence.)
AD9272