ADSP-21160NCB-100 Analog Devices Inc, ADSP-21160NCB-100 Datasheet - Page 26

• Manufacturer Part Number: ADSP-21160NCB-100
• Description: IC,DSP,32-BIT,CMOS,BGA,400PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21160NCB-100

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.90V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Package: 400BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 100 MHz
• Ram Size: 512 KB
• Device Million Instructions Per Second: 100 MIPS

ADSP-21160M/ADSP-21160N
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to
memories (and memory-mapped peripherals) without reference
to CLKIN accept for the ACK pin requirements listed in note 6
Table 18. Memory Read—Bus Master
1
2
3
4
5
6
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
W = (number of wait states specified in WAIT register) × t
HI = t
H = t
Data Delay/Setup: User must meet t
The falling edge of MSx, BMS is referenced.
For ADSP-21160M, specification is t
For ADSP-21160M, specification is 0.75t
Data Hold: User must meet t
For asynchronous access, ACK is sampled only after the programmed wait states for the access have been counted. For the first CLKIN cycle of a new external memory
DAD
DRLD
HDA
SDS
HDRH
DAAK
DSAK
SAKC
HAKC
DRHA
DARL
RW
RWR
capacitive and dc loads.
access, ACK must be driven low (deasserted) by t
t
HAKC
CK
CK
must be met for both assertion and deassertion of ACK signal.
(if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
Address, CIF, Selects Delay to Data Valid
RDx Low to Data Valid
Data Hold from Address, Selects
Data Setup to RDx High
Data Hold from RDx High
ACK Delay from Address, Selects
ACK Delay from RDx Low
ACK Setup to CLKIN
ACK Hold After CLKIN
Address, CIF, Selects Hold After RDx High
Address, CIF, Selects to RDx Low
RDx Pulsewidth
RDx High to WRx, RDx, DMAGx Low
HDA
or t
DAD
HDRH
CK
–0.25t
, t
CK
DRLD
in asynchronous access mode. See Example System Hold Time Calculation on page
–11+W ns, maximum.
CCLK
, or t
6
–11+W ns, maximum.
DAAK
SDS
1, 4
.
1
, t
6
5
DSAK
, or t
Rev. B | Page 26 of 60 | February 2010
5
2
2, 6
SAKC
. For the second and subsequent cycles of an asynchronous external memory access, the t
CK
.
1, 2, 3
Min
0
8
1
0.5t
1
0.25t
0.25t
t
0.5t
CK
– 0.5t
CCLK
CCLK
of
is the bus master accessing external memory space in asynchro-
nous access mode.
CCLK
CCLK
Table
+3
– 1+HI
CCLK
– 3
– 1+H
– 1+W
18. These specifications apply when the ADSP-21160x
Max
t
t
t
t
CK
CK
CK
CK
– 0.75t
– 0.25t
– 0.5t
– 0.5t
49
for the calculation of hold times given
CCLK
CCLK
CCLK
CCLK
– 12+W
+W
– 8.5+W
– 11+W
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SAKC
and