ADSP-21160NCB-100 Analog Devices Inc, ADSP-21160NCB-100 Datasheet - Page 8

• Manufacturer Part Number: ADSP-21160NCB-100
• Description: IC,DSP,32-BIT,CMOS,BGA,400PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21160NCB-100

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.90V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Package: 400BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 100 MHz
• Ram Size: 512 KB
• Device Million Instructions Per Second: 100 MIPS

ADSP-21160M/ADSP-21160N
controlled by the BMS (Boot Memory Select), EBOOT (EPROM
Boot), and LBOOT (Link/Host Boot) pins. 32-bit and 16-bit
host processors can be used for booting.
Phase-Locked Loop
The processor uses an on-chip PLL to generate the internal
clock for the core. Ratios of 2:1, 3:1, and 4:1 between the core
and CLKIN are supported. The CLK_CFG pins are used to
select the ratio. The CLKIN rate is the rate at which the synchro-
nous external port operates.
Power Supplies
The processor has separate power supply connections for the
internal (V
AGND) power supplies. The internal and analog supplies must
meet the V
must meet the 3.3 V requirement. All external supply pins must
be connected to the same supply.
The PLL filter,
in the system. V
mended that the capacitors be connected directly to AGND
using short thick trace. It is recommended that the capacitors be
placed as close to AV
from AGND to the (digital) ground plane should be made after
the capacitors. The use of a thick trace for AGND is reasonable
only because the PLL is a relatively low power circuit—it does
not apply to any other ADSP-21160x GND connection.
DEVELOPMENT TOOLS
The ADSP-21160x is supported with a complete set of
CROSSCORE
including Analog Devices emulators and the VisualDSP++
development environment. The same emulator hardware that
supports other ADSP-2116x processors also fully emulates the
ADSP-21160x.
The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge-
braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ run-time library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
†
‡
CROSSCORE is a registered trademark of Analog Devices, Inc.
VisualDSP++ is a registered trademark of Analog Devices, Inc.
V
DDINT
Figure 6. Analog Power (AV
DDINT
DDINT
®†
Figure
), external (V
DDINT
software and hardware development tools,
and AV
10
0.1 F
DD
is the digital core supply. It is recom-
6, must be added for each ADSP-21160x
and AGND as possible. The connection
DD
AGND
requirement. The external supply
DDEXT
DD
0.01 F
), and analog (AV
) Filter Circuit
AV
DD
Rev. B | Page 8 of 60 | February 2010
DD
and
®‡
translation of C/C++ code to DSP assembly. The DSP has archi-
tectural features that improve the efficiency of compiled C/C++
code.
The VisualDSP++ debugger has a number of important fea-
tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa-
tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com-
plexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Sta-
tistical profiling enables the programmer to nonintrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and effi-
ciently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:
The VisualDSP++ integrated development and debugging envi-
ronment (IDDE) lets programmers define and manage DSP
software development. Its dialog boxes and property pages let
programmers configure and manage all of the Blackfin develop-
ment tools, including the color syntax highlighting in the
VisualDSP++ editor. This capability permits programmers to:
The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem-
ory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning, when
developing new application code. The VDK features include
threads, critical and unscheduled regions, semaphores, events,
and device flags. The VDK also supports priority-based, pre-
emptive, cooperative, and time-sliced scheduling approaches. In
addition, the VDK was designed to be scalable. If the application
does not use a specific feature, the support code for that feature
is excluded from the target system.
• View mixed C/C++ and assembly code (interleaved source
• Insert breakpoints
• Set conditional breakpoints on registers, memory,
• Trace instruction execution
• Perform linear or statistical profiling of program execution
• Fill, dump, and graphically plot the contents of memory
• Perform source level debugging
• Create custom debugger windows
• Control how the development tools process inputs and
• Maintain a one-to-one correspondence with the tool’s
and object information)
and stacks
generate outputs
command line switches