ADUC7036DCPZ-RL Analog Devices Inc, ADUC7036DCPZ-RL Datasheet - Page 12
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ADUC7036DCPZ-RL
Manufacturer Part Number
ADUC7036DCPZ-RL
Description
SFlash 96k ARM7 Dual 16-Bit ADC LIN I.C.
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet
1.EVAL-ADUC7036QSPZ.pdf
(132 pages)
Specifications of ADUC7036DCPZ-RL
Core Processor
ARM7
Core Size
16/32-Bit
Speed
20.48MHz
Connectivity
LIN, SPI, UART/USART
Peripherals
PSM, Temp Sensor, WDT
Number Of I /o
9
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 18 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 115°C
Package / Case
48-VFQFN Exposed Pad, CSP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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ADuC7036
Table 4. SPI Slave Mode Timing—Phase Mode = 1
Parameter
t
t
t
t
t
t
t
t
t
t
t
1
2
SS
SL
SH
DAV
DSU
DHD
DF
DR
SR
SF
SFS
t
t
HCLK
UCLK
depends on the clock divider (CD) bits in the POWCON MMR. t
= 48.8 ns. It corresponds to the 20.48 MHz internal clock from the PLL before the clock divider.
(POLARITY = 0)
(POLARITY = 1)
Description
SS to SCLK edge
SCLK low pulse width
SCLK high pulse width
Data output valid after SCLK edge
Data input setup time before SCLK edge
Data input hold time after SCLK edge
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
SS high after SCLK edge
SCLK
SCLK
MISO
MOSI
SS
t
SS
1
1
t
DAV
t
SH
Figure 4. SPI Slave Mode Timing—Phase Mode = 1
2
t
DSU
2
MSB IN
HCLK
t
MSB
DHD
= t
t
Rev. C | Page 12 of 132
SL
UCLK
/2
t
DF
CD
Min
0
4 × t
.
UCLK
t
DR
BITS[6:1]
BITS[6:1]
Typ
0.5 t
(SPIDIV + 1) × t
(SPIDIV + 1) × t
3.5
3.5
3.5
3.5
0.5 t
SL
SL
t
SR
HCLK
HCLK
LSB IN
t
SF
LSB
Max
(3 × t
t
SFS
UCLK
) + (2 × t
HCLK
)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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