ADUC7036DCPZ-RL Analog Devices Inc, ADUC7036DCPZ-RL Datasheet - Page 63

• Manufacturer Part Number: ADUC7036DCPZ-RL
• Description: SFlash 96k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7036DCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-VFQFN Exposed Pad, CSP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The operating mode, clocking mode, and programmable clock
divider are controlled using two MMRs, PLLCON and POWCON,
and the status of the PLL is indicated by PLLSTA. PLLCON
controls the operating mode of the clock system, and POWCON
controls both the core clock frequency and the power-down mode.
PLLSTA indicates the presence of an oscillator on the XTAL1 pin
and provides information about the PLL lock status and the PLL
interrupt.
Before powering down the ADuC7036, it is recommended that the
clock source for the PLL be switched to the low power 131 kHz
oscillator to reduce wake-up time. The low power oscillator is
always active.
When the ADuC7036 wakes up from power-down, the MCU
core begins executing code as soon as the PLL starts oscillating.
This code execution occurs before the PLL has locked to a fre-
quency of 20.48 MHz. To ensure that the Flash/EE memory
controller is executing with a valid clock, the controller is driven
with a PLL output divide-by-8 clock source while the PLL is
locking. When the PLL locks, the PLL output is switched from
the PLL output divide-by-8 to the locked PLL output.
If user code requires an accurate PLL output, user code must poll
the PLL lock status bit (PLLSTA[1]) after a wake-up before
resuming normal code execution.
The PLL is locked within 2 ms if the PLL is clocked from an
active clock source, such as a low power 131 kHz oscillator,
after waking up.
PLLCON is a protected MMR with two 32-bit keys: PLLKEY0
(prewrite key) and PLLKEY1 (postwrite key). They key values
are as follows:
PLLKEY0 = 0x000000AA
PLLKEY1 = 0x00000055
POWCON is a protected MMR with two 32-bit keys: POWKEY0
(prewrite key) and POWKEY1 (postwrite key).
POWKEY0 = 0x00000001
POWKEY1 = 0x000000F4
Rev. C | Page 63 of 132
An example of writing to both MMRs is as follows:
POWKEY0
POWCON
POWKEY1
iA1*iA2
clear the pipeline, where iA1 and iA2 are
defined as longs and are not 0
PLLKEY0
PLLCON
Power Osc.
PLLKEY1
iA1*iA2
prevent Flash/EE access during clock change
SYSTEM CLOCK REGISTERS
PLLSTA Register
Name: PLLSTA
Address: 0xFFFF0400
Default Value: N/A
Access: Read only
Function: This 8-bit register allows user code to monitor the
lock state of the PLL and the status of the external crystal.
Table 44. PLLSTA MMR Bit Designations
Bit
7 to 3
2
1
0
Description
Reserved.
XTAL clock. This read only bit is a live representation of
the current logic level on XTAL1. It indicates if an external
clock source is present by alternating between high and
low at a frequency of 32.768 kHz.
PLL lock status bit. This is a read only bit.
Set when the PLL is locked and outputting 20.48 MHz.
Cleared when the PLL is not locked and outputting an
f
PLL interrupt.
Set if the PLL lock status bit signal goes low.
Cleared by writing 1 to this bit.
CORE
divide-by-8 clock source.
=
=
=
=
=
=
0x01
0x00
0xF4
0xAA
0x0
0x55
//POWCON key
//Full power-down
//POWCON KEY
//Dummy cycle to
//PLLCON key
//Switch to Low
//PLLCON key
//Dummy cycle to
ADuC7036