ADUC7036DCPZ-RL Analog Devices Inc, ADUC7036DCPZ-RL Datasheet - Page 8

• Manufacturer Part Number: ADUC7036DCPZ-RL
• Description: SFlash 96k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7036DCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-VFQFN Exposed Pad, CSP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ADuC7036
Parameter
LIN VERSION 1.3 SPECIFICATION
LIN VERSION 2.0 SPECIFICATION
BSD INPUT/OUTPUT
WAKE UP
SERIAL TEST INTERFACE
Symmetry of Transmit Propagation
Symmetry of Receive Propagation
R
V
Receive Propagation Delay
D1
D2
Baud Rate
Input leakage current
V
V
I
V
V
VDD
Input Leakage Current
V
V
V
V
Monoflop Timeout
I
Baud Rate
Input Leakage Current
VDD
V
V
V
V
O(SC)
O(SC)
SLAVE
SERIAL DIODE
OL
OH
INL
INH
OH
OL
IH
IL
OH
OL
IH
IL
Delay
Delay
, Output Low Voltage
30
, Output High Voltage
, Input Low Voltage
30
, Input High Voltage
Short-Circuit Output Current
Short-Circuit Output Current
1
t
1
1
dV
SYM
dV
dt
dt
28
1
1
1
29
1
Test Conditions/Comments
Slave termination resistance
Voltage drop at the serial diode, D
VDD (min) = 7 V
VDD (min) = 7 V
VDD (min) = 7 V
Bus load conditions (C
6.8 nF||660 Ω; 10 nF||500 Ω
Slew rate
Dominant and recessive edges, VBAT = 18 V
Slew rate
Dominant and recessive edges, VBAT = 7 V
Symmetry of rising and falling edge, VBAT = 18 V
Symmetry of rising and falling edge, VBAT = 7 V
Bus load conditions (C
6.8 nF||660 Ω; 10 nF||500 Ω
Duty Cycle 1,
TH
TH
V
D1 = t
Duty Cycle 2,
TH
TH
V
D2 = t
Input high = VDD, or input low = IO_VSS
V
R
Supply voltage range at which the WU pin is
functional
Input high = VDD
Input low = IO_VSS
Output high level
Output low level
Input high level
Input low level
Timeout period
R
Input high = VDD or input low = IO_VSS
Supply voltage range for which STI is functional
Output high level
Output low level
Input high level
Input low level
SUP
SUP
BSD
LOAD
LOAD
REC (MAX)
DOM (MAX)
REC (MIN)
DOM (MIN)
= VDD = 12 V
= 7 V…18 V; t
= 7 V…18 V; t
= 300 Ω, C
= 500 Ω, C
BUS_REC (MIN)
BUS_REC (MAX)
= 0.284 × VBAT,
= 0.744 × VBAT,
= 0.422 × VBAT,
= 0.581 × VBAT,
BUS
BUS
/(2 × t
/(2 × t
= 91 nF, R
= 2.4 nF, R
BIT
BIT
= 50 μs,
= 50 μs,
BUS
BIT
BIT
Rev. C | Page 8 of 132
BUS
)
||R
)
||R
BUS
LIMIT
BUS
LIMIT
):1 nF||1 kΩ;
): 1 nF||1 kΩ;
= 39 Ω
= 39 Ω
SER_INT
0.4
−2
−2
1
0.5
−5
−4
0.396
0.8 VDD
50
0.7 VDD
7
0.4
−50
5
4.6
7
0.6 VDD
0.6 VDD
Min
20
1164
−50
0.6
100
−50
Typ
30
0.7
2
1200
80
1.3
140
Max
47
1
+2
6
+2
3
3
+5
+4
0.581
1236
+50
1.2
120
1.8
18
2.1
+50
2
1.2
2
40
+70
18
0.4 VDD
0.4 VDD
Unit
kΩ
V
μs
μs
μs
V/μs
V/μs
μs
μs
Bits/sec
μA
V
V
mA
V
V
V
mA
μA
V
V
V
V
sec
mA
kbps
μA
V
V
V
V
V