ADUC7060BCPZ32 Analog Devices Inc, ADUC7060BCPZ32 Datasheet - Page 23

• Manufacturer Part Number: ADUC7060BCPZ32
• Description: DUAL 24-BIT AFE AND ARM 7 I.C
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7060BCPZ32

• Design Resources: 4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145) Low power, Long Range, ISM Wireless Measuring Node (CN0164)
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 14
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 2.625 V
• Data Converters: A/D 5x24b, 8x24b, D/A 1x14b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

By default, after a reset, the Flash/EE memory is logically
mapped to Address 0x00000000. It is possible to logically remap
the SRAM to Address 0x00000000 by setting Bit 0 of the remap
MMR located at 0xFFFF0220. To revert Flash/EE to 0x00000000,
Bit 0 of remap is cleared.
It is sometimes desirable to remap RAM to 0x00000000 to optimize
the interrupt latency of the ADuC706x because code can run in
full 32-bit ARM mode and at maximum core speed. Note that,
when an exception occurs, the core defaults to ARM mode.
Remap Operation
When a reset occurs on the ADuC706x, execution starts automati-
cally in the factory programmed internal configuration code.
This so-called kernel is hidden and cannot be accessed by user
code. If the ADuC706x is in normal mode, it executes the power-
on configuration routine of the kernel and then jumps to the
reset vector, Address 0x00000000, to execute the user’s reset
exception routine. Because the Flash/EE is mirrored at the
bottom of the memory array at reset, the reset routine must
always be written in Flash/EE.
The remap command must be executed from the absolute Flash/EE
address and not from the mirrored, remapped segment of memory,
because this may be replaced by SRAM. If a remap operation is
executed while operating code from the mirrored location, pre-
fetch/data aborts can occur, or the user can observe abnormal
program operation. Any kind of reset logically remaps the Flash/EE
memory to the bottom of the memory array.
Remap Register
Name:
Address:
Default value:
Access:
Function:
Table 12. Remap MMR Bit Designations
Bit
7:1
0
FLASH/EE CONTROL INTERFACE
Serial and JTAG programming use the Flash/EE control
interface, which includes the eight MMRs outlined in this
section. Note that the flash page size is 512 bytes.
Description
Reserved. These bits are reserved and should be written
as 0 by user code.
Remap bit.
Set by user to remap the SRAM to 0x00000000.
Cleared automatically after reset to remap the Flash/EE
memory to 0x00000000.
Remap
0xFFFF0220
0x0000
Read and write
This 8-bit register allows user code to remap
either RAM or Flash/EE space into the bottom
of the ARM memory space starting at
Address 0x00000000.
Rev. B | Page 23 of 108
FEESTA Register
FEESTA is a read-only register that reflects the status of the
flash control interface as described in Table 13.
Name:
Address:
Default value:
Access:
Table 13. FEESTA MMR Bit Designations
Bit
15:6
5
4
3
2
1
0
FEEMOD Register
FEEMOD sets the operating mode of the flash control interface.
Table 14 lists FEEMOD MMR bit designations.
Name:
Address:
Default value:
Access:
Table 14. FEEMOD MMR Bit Designations
Bit
15:9
8
7:5
4
3
2:0
Description
Reserved.
Reserved.
Reserved.
Flash interrupt status bit. Set automatically when an
interrupt occurs, that is, when a command is complete
and the Flash/EE interrupt enable bit in the FEEMOD
register is set. Cleared when reading the FEESTA
register.
Flash/EE controller busy. Set automatically when the
controller is busy. Cleared automatically when the
controller is not busy.
Command fail. Set automatically when a command
completes unsuccessfully. Cleared automatically when
reading the FEESTA register.
Command pass. Set by the MicroConverter® when a
command completes successfully. Cleared
automatically when reading the FEESTA register.
Description
Reserved.
Reserved. Always set this bit to 1.
Reserved. Always set these bits to 0 except when
writing keys.
Flash/EE interrupt enable.
Set by user to enable the Flash/EE interrupt. The
interrupt occurs when a command is complete.
Cleared by user to disable the Flash/EE interrupt.
Erase/write command protection.
Set by user to enable the erase and write commands.
Cleared to protect the Flash/EE against the erase/write
command.
Reserved. Always set these bits to 0.
FEESTA
0xFFFF0E00
0x0020
Read
FEEMOD
0xFFFF0E04
0x0000
Read and write
ADuC7060/ADuC7061