ADUC7060BCPZ32 Analog Devices Inc, ADUC7060BCPZ32 Datasheet - Page 24
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ADUC7060BCPZ32
Manufacturer Part Number
ADUC7060BCPZ32
Description
DUAL 24-BIT AFE AND ARM 7 I.C
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet
1.EVAL-ADUC7061MKZ.pdf
(108 pages)
Specifications of ADUC7060BCPZ32
Design Resources
4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145) Low power, Long Range, ISM Wireless Measuring Node (CN0164)
Core Processor
ARM7
Core Size
16/32-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
14
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.375 V ~ 2.625 V
Data Converters
A/D 5x24b, 8x24b, D/A 1x14b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
32-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ADuC7060/ADuC7061
FEECON Register
FEECON is an 8-bit command register. The commands are
described in Table 15.
Table 15. Command Codes in FEECON
Code
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
1
The FEECON register always reads 0x07 immediately after execution of any of these commands.
1
1
1
1
1
1
1
Command
Null
Single read
Single write
Erase/write
Single verify
Single erase
Mass erase
Reserved
Reserved
Reserved
Reserved
Signature
Protect
Reserved
Reserved
Ping
Description
Idle state.
Write FEEDAT at the address pointed to by FEEADR. This operation takes 50 μs.
Erase the page indexed by FEEADR and write FEEDAT at the location pointed to by FEEADR. This operation takes
approximately 24 ms.
Compare the contents of the location pointed to by FEEADR to the data in FEEDAT. The result of the
comparison is returned in FEESTA Bit 0 and Bit 1.
Erase the page indexed by FEEADR.
Erase 30 kB of user space. The 2 kB of kernel are protected. To prevent accidental execution, a command
sequence is required to execute this instruction. See the Command Sequence for Executing a Mass Erase
section.
Reserved.
Reserved.
Reserved.
Reserved.
This command results in a 24-bit LFSR-based signature being generated and loaded into the FEESIGN MMR.
This operation takes 16,389 clock cycles.
This command can run only once. The value of FEEPRO is saved and is removed only with a mass erase (0x06)
or the key.
Reserved.
Reserved.
No operation; interrupt generated.
Load FEEDAT with the 16-bit data. Indexed by FEEADR.
Rev. B | Page 24 of 108
Name:
Address:
Default value:
Access:
FEECON
0xFFFF0E08
0x07
Read and write