ADUC7060BCPZ32 Analog Devices Inc, ADUC7060BCPZ32 Datasheet - Page 83

• Manufacturer Part Number: ADUC7060BCPZ32
• Description: DUAL 24-BIT AFE AND ARM 7 I.C
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7060BCPZ32

• Design Resources: 4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145) Low power, Long Range, ISM Wireless Measuring Node (CN0164)
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 14
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 2.625 V
• Data Converters: A/D 5x24b, 8x24b, D/A 1x14b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UART Status Register 1
COMSTA1 Register
Name:
Address:
Default value:
Access:
Function:
Table 92. COMSTA1 MMR Bit Designations
Bit
7:5
4
3:1
0
UART Interrupt Enable Register 0
COMIEN0 Register
Name:
Address:
Default value:
Access:
Function:
Name
CTS
DCTS
Description
Reserved. Not used.
Clear to send.
Reserved. Not used.
Delta CTS.
Set automatically if CTS changed state since
COMSTA1 was last read.
Cleared automatically by reading COMSTA1.
COMSTA1
0x00
Read only
COMSTA1 is a modem status register.
COMIEN0
0x00
Read and write
individual UART interrupt sources.
0xFFFF0718
0xFFFF0704
This 8-bit register enables and disables the
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Table 93. COMIEN0 MMR Bit Designations
Bit
7:4
3
2
1
0
UART Interrupt Identification Register 0
COMIID0 Register
Name:
Address:
Default value:
Access:
Function:
Name
EDSSI
ELSI
ETBEI
ERBFI
COMIID0
0xFFFF0708
0x01
Read only
This 8-bit register reflects the source of the
UART interrupt.
Description
Reserved. Not used.
Modem status interrupt enable bit.
Set by user to enable generation of an
interrupt if any of COMSTA0[3:1] are set.
Cleared by user.
Receive status interrupt enable bit.
Set by user to enable generation of an
interrupt if any of the COMSTA0[3:1] register
bits are set.
Cleared by user.
Enable transmit buffer empty interrupt.
Set by user to enable an interrupt when the
buffer is empty during a transmission; that is,
when COMSTA0[5] is set.
Cleared by user.
Enable receive buffer full interrupt.
Set by user to enable an interrupt when the
buffer is full during a reception.
Cleared by user.
ADuC7060/ADuC7061