CS47048C-CQZ Cirrus Logic Inc, CS47048C-CQZ Datasheet - Page 22
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CS47048C-CQZ
Manufacturer Part Number
CS47048C-CQZ
Description
IC 4CH ADC 8ch DAC & 32bit DSP
Manufacturer
Cirrus Logic Inc
Type
Fixed Pointr
Specifications of CS47048C-CQZ
Interface
I²C, SPI
Clock Rate
150MHz
On-chip Ram
128kB
Voltage - I/o
3.30V
Voltage - Core
1.80V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-LQFP Exposed Pad, 100-eLQFP, 100-HLQFP
Operating Temperature Range
0°C To +70°C
No. Of Pins
100
Frequency
147MHz
Embedded Interface Type
I2C, SPI
Core Supply Voltage
1.89V
No. Of Mips
150
Digital Ic Case Style
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1539 - BOARD EVAL 4CH ADC/8CH DAC DSP598-1536 - BOARD EVAL 4CH ADC/8CH DAC DSP
Non-volatile Memory
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
598-1657
CS47048B-CQZ
CS47048B-CQZ
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CS47048C-CQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
135
Company:
Part Number:
CS47048C-CQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Company:
Part Number:
CS47048C-CQZR
Manufacturer:
CIRRUS
Quantity:
1 400
Company:
Part Number:
CS47048C-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
CS47048C-CQZR
Manufacturer:
CIRRUSLOGIC
Quantity:
20 000
CS470xx Data Sheet
Audio SOC Processor Family
5.11 Digital Switching Characteristics — Serial Control Port - I
22
SCP_CLK frequency
SCP_CLK rise time
SCP_CLK fall time
SCP_CLK low time
SCP_CLK high time
SCP_CLK rising to SCP_SDA rising or falling for
START or STOP condition
START condition to SCP_CLK falling
SCP_CLK falling to STOP condition
Bus free time between STOP and START conditions
Setup time SCP_SDA input valid to SCP_CLK rising
Hold time SCP_SDA input after SCP_CLK falling
SCP_CLK low to SCP_SDA out valid
SCP_CLK falling to SCP_IRQ rising
NAK condition to SCP_IRQ low
SCP_CLK rising to SCB_BSY low
1. f
I
2
C Slave Address = 0x82
speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY pin
should be implemented to prevent overflow of the input data buffer.
SCP_BSY
iicck
SCP_IRQ
SCP_CLK
SCP_SDA
indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum
t
iicstscl
t
1
Parameter
iicckcmd
Figure 9.
t
iicsu
Start Condition
A6
0
t
iich
1
Serial Control Port - I
t
iicckh
t
iicckl
Copyright 2011 Cirrus Logic
A0
6
t
iicr
R/W
7
t
iicdov
Symbol
t
iicckcmd
t
t
t
t
t
iicstscl
t
t
t
t
iicbsyl
f
t
iicirqh
iicckh
iicdov
iicstp
iicirql
ACK
iicckl
t
t
iicbft
iicsu
iicck
t
iich
iicr
iicf
8
t
iicf
2
C Slave Mode Timing
MSB
1.25
1.25
1.25
1.25
Min
100
0
110
2.5
3
-
-
-
-
1
1/
3
3
*
*
f
iicck
DCLKP + 20
DCLKP + 20
t
Typical
iicirqh
2
6
C Slave Mode
LSB
7
3
t
*
iiccbsyl
DCLKP + 40
ACK
8
Max
400
150
150
18
-
-
-
-
-
-
t
t
iicirql
iicstp
t
iicckcmd
DS787PP5
Stop Condition
Units
t
kHz
iicbft
ns
ns
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns