CY7C1412AV18-200BZC Cypress Semiconductor Corp, CY7C1412AV18-200BZC Datasheet - Page 6

• Manufacturer Part Number: CY7C1412AV18-200BZC
• Description: SRAM (Static RAM)
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1412AV18-200BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 36M (2M x 18)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Functional Overview
The CY7C1412AV18, and CY7C1414AV18 are synchronous
pipelined Burst SRAMs with a read port and a write port. The
read port is dedicated to read operations and the write port is
dedicated to write operations. Data flows into the SRAM through
the write port and flows out through the read port. These devices
multiplex the address inputs to minimize the number of address
pins required. By having separate read and write ports, the
QDR-II completely eliminates the need to “turn around” the data
bus and avoids any possible data contention, thereby simplifying
system design. Each access consists of two 18 bit data transfers
in the case of CY7C1412AV18, and two 36 bit data transfers in
the case of CY7C1414AV18 in one clock cycle.
Accesses for both ports are initiated on the rising edge of the
positive input clock (K). All synchronous input timing is
referenced from the rising edge of the input clocks (K and K) and
all output timing is referenced to the rising edge of the output
clocks (C and C, or K and K when in single clock mode).
All synchronous data inputs (D
controlled by the input clocks (K and K). All synchronous data
outputs (Q
rising edge of the output clocks (C and C, or K and K when in
single clock mode).
All synchronous control (RPS, WPS, BWS
through input registers controlled by the rising edge of the input
clocks (K and K).
CY7C1412AV18 is described in the following sections. The same
basic descriptions apply to CY7C1414AV18.
Read Operations
The CY7C1412AV18 is organized internally as two arrays of 1M
x 18. Accesses are completed in a burst of two sequential 18 bit
data words. Read operations are initiated by asserting RPS
active at the rising edge of the positive input clock (K). The
address is latched on the rising edge of the K clock. The address
presented to the address inputs is stored in the read address
register. Following the next K clock rise the corresponding lowest
order 18 bit word of data is driven onto the Q
output timing reference. On the subsequent rising edge of C, the
next 18 bit data word is driven onto the Q
data is valid 0.45 ns from the rising edge of the output clock (C
and C or K and K when in single clock mode).
Synchronous internal circuitry automatically tri-states the outputs
following the next rising edge of the output clocks (C/C). This
allows for a seamless transition between devices without the
insertion of wait states in a depth expanded memory.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the same K clock
rise, the data presented to D
lower 18 bit write data register, provided BWS
asserted active. On the subsequent rising edge of the negative
input clock (K), the address is latched and the information
Document #: 38-05615 Rev. *H
[x:0]
) pass through output registers controlled by the
[17:0]
[x:0]
) pass through input registers
is latched and stored into the
[17:0]
[17:0]
[x:0]
. The requested
) inputs pass
using C as the
[1:0]
are both
presented to D
BWS
written into the memory array at the specified location. When
deselected, the write port ignores all inputs after completion of
pending write operations.
Byte Write Operations
Byte write operations are supported by the CY7C1412AV18. A
write operation is initiated as described in the
section. The bytes that are written are determined by BWS
BWS
the appropriate Byte Write Select input during the data portion of
a write latches the data being presented and writes it into the
device. Deasserting the Byte Write Select input during the data
portion of a write allows the data stored in the device for that byte
to remain unaltered. This feature can be used to simplify read,
modify, or write operations to a byte write operation.
Single Clock Mode
The CY7C1412AV18 can be used with a single clock that
controls both the input and output registers. In this mode, the
device recognizes only a single pair of input clocks (K and K) that
control both the input and output registers. This operation is
identical to the operation if the device had zero skew between
the K/K and C/C clocks. All timing parameters remain the same
in this mode. To use this mode of operation, the user must tie C
and C HIGH at power on. This function is a strap option and not
alterable during device operation.
Concurrent Transactions
The read and write ports on the CY7C1412AV18 operate
independently of one another. As each port latches the address
inputs on different clock edges, the user can read or write to any
location, regardless of the transaction on the other port. The user
can start reads and writes in the same clock cycle. If the ports
access the same location at the same time, the SRAM delivers
the most recent information associated with the specified
address location. This includes forwarding data from a write
cycle that was initiated on the previous K clock rise.
Depth Expansion
The CY7C1412AV18 has a port select input for each port. This
enables for easy depth expansion. Both port selects are sampled
on the rising edge of the positive input clock only (K). Each port
select input can deselect the specified port. Deselecting a port
does not affect the other port. All pending transactions (read and
write) are completed prior to the device being deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and V
driver impedance. The value of RQ must be 5x the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175 and 350
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.
[1:0]
1
, which are sampled with each 18 bit data word. Asserting
are both asserted active. The 36 bits of data are then
[17:0]
is stored into the write data register, provided
SS
to allow the SRAM to adjust its output
CY7C1412AV18
CY7C1414AV18
,
with V
Write Operations
DDQ
Page 6 of 27
= 1.5V. The
0
and
[+] Feedback