CY7C68013A-56LTXCT Cypress Semiconductor Corp, CY7C68013A-56LTXCT Datasheet - Page 43

• Manufacturer Part Number: CY7C68013A-56LTXCT
• Description: CY7C68013A-56LTXCT
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX2LP™r

Specifications of CY7C68013A-56LTXCT

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 24
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Processor Series: CY7C68xx
• Core: 8051
• Development Tools By Supplier: CY3684
• Package: 56QFN EP
• Device Core: 8051
• Family Name: FX2LP
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 24
• Interface Type: I2C/USART/USB
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4611B - KIT USB TO ATA REFERENCE DESIGN428-1677 - KIT DEVELOPMENT EZ-USB FX2LP
• Lead Free Status / Rohs Status: Details

9.6 GPIF Synchronous Signals
Table 17. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK
Table 18. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK
Document #: 38-08032 Rev. *U
Notes
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
IFCLK
SRY
RYH
SGD
DAH
SGA
XGD
XCTL
IFCLKR
IFCLKF
IFCLKOD
IFCLKJ
IFCLK
SRY
RYH
SGD
DAH
SGA
XGD
XCTL
20. Dashed lines denote signals with programmable polarity.
21. GPIF asynchronous RDY
22. IFCLK must not exceed 48 MHz.
Parameter
Parameter
IFCLK Period
RDY
Clock to RDY
GPIF Data to Clock Setup Time
GPIF Data Hold Time
Clock to GPIF Address Propagation Delay
Clock to GPIF Data Output Propagation Delay
Clock to CTL
IFCLK rise time
IFCLK fall time
IFCLK Output duty cycle
IFCLK jitter peak to peak
x
signals have a minimum setup time of 50 ns when using internal 48 MHz IFCLK.
IFCLK Period
RDY
Clock to RDY
GPIF Data to Clock Setup Time
GPIF Data Hold Time
Clock to GPIF Address Propagation Delay
Clock to GPIF Data Output Propagation Delay
Clock to CTL
X
to Clock Setup Time
GPIFADR[8:0]
DATA(output)
X
DATA(input)
to Clock Setup Time
Figure 9-6. GPIF Synchronous Signals Timing Diagram
X
X
IFCLK
RDY
CTL
Output Propagation Delay
X
Description
[22]
X
X
X
Output Propagation Delay
Description
t
SRY
t
SGD
t
XCTL
N
t
XGD
t
IFCLK
valid
t
RYH
t
t
DAH
SGA
N+1
20.83
Min
8.9
9.2
0
0
–
–
–
–
–
–
–
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
[20, 21]
[21]
Max
7.5
6.7
11
20.83
–
–
–
–
–
–
–
–
–
Min
2.9
3.7
3.2
4.5
–
–
–
[20]
Min
49
–
–
–
–
–
–
–
–
–
–
–
10.7
Max
11.5
200
15
Typ
–
–
–
–
Max
900
900
300
51
–
–
–
–
–
–
–
–
Page 43 of 67
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
%
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