CY7C68013A-56LTXCT Cypress Semiconductor Corp, CY7C68013A-56LTXCT Datasheet - Page 62

• Manufacturer Part Number: CY7C68013A-56LTXCT
• Description: CY7C68013A-56LTXCT
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX2LP™r

Specifications of CY7C68013A-56LTXCT

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 24
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Processor Series: CY7C68xx
• Core: 8051
• Development Tools By Supplier: CY3684
• Package: 56QFN EP
• Device Core: 8051
• Family Name: FX2LP
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 24
• Interface Type: I2C/USART/USB
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4611B - KIT USB TO ATA REFERENCE DESIGN428-1677 - KIT DEVELOPMENT EZ-USB FX2LP
• Lead Free Status / Rohs Status: Details

12. PCB Layout Recommendations
Follow these recommendations to ensure reliable high
performance operation:
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Document #: 38-08032 Rev. *U
Note
25. Source for recommendations: EZ-USB FX2™PCB Design Recommendations,
Four layer impedance controlled boards are required to
maintain signal quality.
Specify impedance targets (ask your board vendor what they
can achieve).
To control impedance, maintain trace widths and trace spacing.
Minimize stubs to minimize reflected signals.
Connections between the USB connector shell and signal
ground must be near the USB connector.
http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf.
[25]
http://www.cypress.com
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Bypass and flyback caps on VBus, near connector, are
recommended.
DPLUS and DMINUS trace lengths should be kept to within
2 mm of each other in length, with preferred length of 20 to
30 mm.
Maintain a solid ground plane under the DPLUS and DMINUS
traces. Do not allow the plane to split under these traces.
Do not place vias on the DPLUS or DMINUS trace routing.
Isolate the DPLUS and DMINUS traces from all other signal
traces by no less than 10 mm.
and High Speed USB Platform Design Guidelines,
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Page 62 of 67
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