DSPIC33FJ16GP101-I/SS Microchip Technology, DSPIC33FJ16GP101-I/SS Datasheet - Page 195
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DSPIC33FJ16GP101-I/SS
Manufacturer Part Number
DSPIC33FJ16GP101-I/SS
Description
16-bit DSC Family, 16 MIPS, 16KB Flash, 1KB RAM 20 SSOP .209in TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet
1.DSPIC33FJ16GP101-IP.pdf
(322 pages)
Specifications of DSPIC33FJ16GP101-I/SS
Processor Series
dsPIC33F
Core
dsPIC
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
16 KB
Interface Type
SPI, I2C, UART, JTAG
Number Of Programmable I/os
35
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Core Processor
dsPIC
Core Size
16-Bit
Speed
16 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
13
Eeprom Size
-
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP (0.209", 5.30mm Width)
Lead Free Status / Rohs Status
Details
- Current page: 195 of 322
- Download datasheet (5Mb)
REGISTER 19-2:
© 2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-13
bit 12-11
bit 10
bit 9-8
bit 7
bit 6
bit 5-2
bit 1
bit 0
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
R/W-0
BUFS
R-0
VCFG<2:0>: Converter Voltage Reference Configuration bits
Unimplemented: Read as ‘0’
CSCNA: Scan Input Selections for CH0+ during Sample A bit
1 = Scan inputs
0 = Do not scan inputs
CHPS<1:0>: Select Channels Utilized bits
1x =Converts CH0, CH1, CH2 and CH3
01 =Converts CH0 and CH1
00 =Converts CH0
BUFS: Buffer Fill Status bit (valid only when BUFM = 1)
1 = ADC is currently filling second half of buffer, user should access data in the first half
0 = ADC is currently filling first half of buffer, user application should access data in the second half
Unimplemented: Read as ‘0’
SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits
1111 =Interrupts at the completion of conversion for each 16th sample/convert sequence
1110 =Interrupts at the completion of conversion for each 15th sample/convert sequence
•
•
•
0001 =Interrupts at the completion of conversion for each 2nd sample/convert sequence
0000 =Interrupts at the completion of conversion for each sample/convert sequence
BUFM: Buffer Fill Mode Select bit
1 = Starts filling first half of buffer on first interrupt and the second half of buffer on next interrupt
0 = Always starts filling buffer from the beginning
ALTS: Alternate Input Sample Mode Select bit
1 = Uses channel input selects for Sample A on first sample and Sample B on next sample
0 = Always uses channel input selects for Sample A
VCFG<2:0>
xxx
R/W-0
U-0
—
AD1CON2: ADC1 CONTROL REGISTER 2
ADREF+
AV
‘1’ = Bit is set
W = Writable bit
DD
R/W-0
R/W-0
ADREF-
AV
R/W-0
Preliminary
U-0
—
SS
SMPI<3:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
U-0
—
CSCNA
R/W-0
R/W-0
x = Bit is unknown
R/W-0
R/W-0
BUFM
CHPS<1:0>
DS70652C-page 195
R/W-0
R/W-0
ALTS
bit 8
bit 0
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