DSPIC33FJ16GP101-I/SS Microchip Technology, DSPIC33FJ16GP101-I/SS Datasheet - Page 211
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DSPIC33FJ16GP101-I/SS
Manufacturer Part Number
DSPIC33FJ16GP101-I/SS
Description
16-bit DSC Family, 16 MIPS, 16KB Flash, 1KB RAM 20 SSOP .209in TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet
1.DSPIC33FJ16GP101-IP.pdf
(322 pages)
Specifications of DSPIC33FJ16GP101-I/SS
Processor Series
dsPIC33F
Core
dsPIC
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
16 KB
Interface Type
SPI, I2C, UART, JTAG
Number Of Programmable I/os
35
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Core Processor
dsPIC
Core Size
16-Bit
Speed
16 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
13
Eeprom Size
-
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP (0.209", 5.30mm Width)
Lead Free Status / Rohs Status
Details
- Current page: 211 of 322
- Download datasheet (5Mb)
REGISTER 20-5:
© 2011 Microchip Technology Inc.
Legend:
R = Readable bit
-n = Value at POR
bit 15-7
bit 6-4
bit 3
bit 2-0
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
bit 15
bit 7
U-0
U-0
—
—
Unimplemented: Read as ‘0’
CFSEL<2:0>: Comparator Filter Input Clock Select bits
111 = Reserved
110 = Reserved
101 = Timer3
100 = Timer2
011 = Reserved
010 = PWM Special Event Trigger
001 = F
000 = F
CFLTREN: Comparator Filter Enable bit
1 = Digital filter enabled
0 = Digital filter disabled
CFDIV<2:0>: Comparator Filter Clock Divide Select bits
111 = Clock Divide 1:128
110 = Clock Divide 1:64
101 = Clock Divide 1:32
100 = Clock Divide 1:16
011 = Clock Divide 1:8
010 = Clock Divide 1:4
001 = Clock Divide 1:2
000 = Clock Divide 1:1
R/W-0
U-0
—
CMxFLTR: COMPARATOR FILTER CONTROL REGISTER
OSC
CY
CFSEL<2:0>
W = Writable bit
‘1’ = Bit is set
R/W-0
U-0
—
R/W-0
U-0
Preliminary
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CFLTREN
R/W-0
U-0
—
R/W-0
U-0
—
CFDIV<2:0>
x = Bit is unknown
R/W-0
U-0
—
DS70652C-page 211
R/W-0
bit 8
bit 0
I-0
—
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