KSZ8842-PMBL Micrel Inc, KSZ8842-PMBL Datasheet - Page 34

• Manufacturer Part Number: KSZ8842-PMBL
• Description: 2-Port Ethernet Switch/Repeater + 32-bit/33MHz PCI Bus Interface ( )
• Manufacturer: Micrel Inc

Specifications of KSZ8842-PMBL

• Controller Type: Ethernet Switch Controller
• Interface: PCI
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFBGA
• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog/Digital
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.5V
• Operating Supply Voltage (min): 3.1V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1636 - BOARD EVALUATION KSZ8842-PMQL
• Current - Supply: -
• Lead Free Status / RoHS Status: Supplier Unconfirmed, Lead free / RoHS Compliant
• Other names: 576-3089

Micrel, Inc.
Bit [8] of registers P1CR4 and P2CR4 is used to enable far-end loop back for ports 1 and 2, respectively. Alternatively,
Bit [14] of registers P1MBCR and P2MBCR can also be used to enable far-end loop back. When register P2MBCR bit
14 =1 or P2CR4 bit 8 =1, the port 2 far-end loop back path is illustrated in the Figure 11.
Near-end (Remote) Loop back:
Near-end (Remote) loop back is conducted at either PHY port 1 or PHY port 2 of the KSZ8842-PMQL/PMBL. The loop
back path starts at the PHY port’s receive inputs (RXPx/RXMx), wraps around at the same PHY port’s PMD/PMA, and
ends at the PHY port’s transmit outputs (TXPx/TXMx).
Bit [1] of registers P1PHYCTRL and P2PHYCTRL is used to enable near-end loop back for ports 1 and 2, respectively.
Alternatively, Bit [9] of registers P1SCSLMD and P2SCSLMD can also be used to enable near-end loop back. Both
ports 1 and 2 near-end loop back paths are illustrated in the following Figure 10.
October 2007
Figure 11. Port 1 and Port 2 Near-End (Remote) Loop back Path
R X P 1 /
R X M 1
R X P
R X P 1 1 1 1 / / / /
R X P
R X P
R X M 1 1 1 1
R X M
R X M
R X M
T X P
T X P
T X P
T X P 2 2 2 2 / / / /
T X M
T X M 2 2 2 2
T X M
T X M
Figure 10. Port 2 Far-End Loop back Path
P M D 2 / P M A 2
P M D 1 / P M A 1
F a r - e n d L o o p b a c k
N e a r
N e a r
N e a r
N e a r - - - - e n d
N e a r
N e a r - - - - e n d
N e a r
N e a r
P M D 2 / P M A 2
P M D 1 / P M A 1
S w i t c h
O r i g i n a t i n g
P H Y
P H Y
M A C 2
M A C 1
P H Y
P H Y
P H Y
P H Y
P H Y
P H Y
P H Y
P H Y
P C S 2
P C S 1
L o o p b a c k
L o o p b a c k
M A C 1
S w i t c h
M A C 2
L o o p b a c k
L o o p b a c k
L o o p b a c k
L o o p b a c k
L o o p b a c k
L o o p b a c k
P C S 1
P C S 2
e n d
e n d
e n d
e n d
e n d
e n d
P o r t 2
P o r t 1
P o r t
P o r t 2 2 2 2
P o r t
P o r t
P o r t
P o r t 1 1 1 1
P o r t
P o r t
34
( ( ( ( r e m o t e
( ( ( ( r e m o t e
r e m o t e
r e m o t e ) ) ) )
r e m o t e ) ) ) )
r e m o t e
r e m o t e
r e m o t e
T X P 1 /
T X M 1
T X P
T X P
T X P
T X P 1 1 1 1 / / / /
T X M 1 1 1 1
T X M
R X P
R X P
R X P
R X P 2 2 2 2 / / / /
T X M
T X M
R X M
R X M 2 2 2 2
R X M
R X M
KSZ8842-PMQL/PMBL
M9999-100207-1.5