CYII4SM1300AA-QDC Cypress Semiconductor Corp, CYII4SM1300AA-QDC Datasheet - Page 23

• Manufacturer Part Number: CYII4SM1300AA-QDC
• Description: SENSOR IMAGE MONO CMOS 84-LCC
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYII4SM1300AA-QDC

• Package / Case: 84-LCC
• Pixel Size: 7µm² x 7µm²
• Active Pixel Array: 1286H x 1030V
• Frames Per Second: 7
• Voltage - Supply: 5V
• Operating Supply Voltage: 5 V
• Image Size: 1280 H x 1024 V
• Color Sensing: Black/White
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: IBIS4-1300-M-2; IBIS4-1300-M-2

Figure 18.
initialization/ blanking sequence.
■
■
■
■
■
■
■
The X-Direction Shift Register
The X shift register behaves like the Y shift registers.
The sequence if initiated by SYNC_X, which should occur when
CLOCK_X is high. As CLOCK_X is halted during the blanking
time, the SYNC_X pulse could occur anywhere, and be taken
equal to some other pulse (e.g. CLOCK_Y).
Document Number: 38-05707 Rev. *C
The EOS_X pulse flags the end of the scanning of previous
line, and should be considered as a diagnostic means only. The
blanking sequence could start earlier or later.
The next row (=line) is selected after the falling edge of CLK_YR
and CLK_YL,
The column amplifiers receive the signals on the pixels array
columns buses when SHY is low (transparent).
The SIN pulse (high) forces the column amplifiers in an “offset
nulling" state.
After 3 us, the column amplifiers have reached offset-free
equilibrium, and the SIN pulse is brought low again. The pixel's
signal level is thus stored in the column amplifier.
After that the pixels in the selected row (line) are be reset (first
pulse on RESET).
Consequently the reset level is frozen in the column amplifiers
when SHY goes high. Both signal level and reset level have
now been applied to the column amplifiers. The sample hold
(SHY) guarantees that this information will not change anymore
during readout of the line.
Figure 19. Pulse on 'CALIB_F'& 'UNITYGAIN' to be Given Once Per Frame, or on CALIB_S Once Per Line
and
Table 9.
Signal applied to
input of amplifier
Calib_s
or
Calib_f
illustrate the timing constraints of the row
100ns
100ns (calib_s)
■
■
During some or the entire row blanking times, the output amplifier
can be calibrated.
If the slow calibration method is used, pulse the 'CALIB_S' pin
once per line. The calibration happens on the rising edge of the
pulse.
If the fast calibration is used, the 'CALIB_F' should be pulsed
during the row blanking time of the first row only. This calibration
happens during the time that the pulse is high.
During this calibration, the input applied to the amplifier must be
the dark reference, which can either be the built-in electrical dark
reference, or an external dark reference on the pin EXTIN.
The first real (dummy) pixel is read out after the 3rd falling edge
on the clock. Dummy pixels are perfectly operational pixels, but
are added to shield the "real" pixels from the cross talk of the
periphery.
"Dark"
reference
Now, the row is ready for readout. A pulse on SYNC_X must
be given to start the row readout. SYNC_X initiates the
X-direction scanning register. The scanning itself is controlled
by CLOCK_X.
During the beginning of the row readout, or possibly before, the
RESET pulse for the electronic shutter (ES) must be given, if
the ES is used. This is a pulse on RESET together with a high
level on L/R. If the ES is not used, L/R remains low and the
second RESET pulse is not generated.
500ns (calib_f)
CYII4SM1300AA
Page 23 of 35
[+] Feedback