CYII4SM1300AA-QDC Cypress Semiconductor Corp, CYII4SM1300AA-QDC Datasheet - Page 9

• Manufacturer Part Number: CYII4SM1300AA-QDC
• Description: SENSOR IMAGE MONO CMOS 84-LCC
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYII4SM1300AA-QDC

• Package / Case: 84-LCC
• Pixel Size: 7µm² x 7µm²
• Active Pixel Array: 1286H x 1030V
• Frames Per Second: 7
• Voltage - Supply: 5V
• Operating Supply Voltage: 5 V
• Image Size: 1280 H x 1024 V
• Color Sensing: Black/White
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: IBIS4-1300-M-2; IBIS4-1300-M-2

Table 2. Pins of the Image Sensor Core (continued)
Output Amplifier
The output amplifier stage is user-programmable for gain and offset level. Gain and offset are controlled by 4-bit wide words. Gain
settings are on an exponential scale. Offset is controlled by a 4-bit wide DAC, which selects the offset voltage between 2 reference
voltages (Vhigh_dac and Vlow_dac) on a linear scale.
The offset setting is independent of the gain setting.
The gain setting is independent of amplifier bandwidth.
The amplifier is designed to match the specifications like the output of the imager array. This signal has a data rate Of 10 MHz and is
located between 1.2 and 2.4V.
Table 3. Summary of Output Amplifier Specifications
The range of the output stage input is between 1 and 4V. A lowest gain the sensor outputs a signal in between 1.2 and 2.2V, which
fits into the input range of the amplifier. The range of the output signal is between 1 and 4.5V, dependent on the gain and offset settings
of the amplifier. This range should fit to the input range of the ADC, external or internal. The on-chip ADC range is between 2 and
4V. A minimal gain setting of "3" seems necessary for the internal ADC, and the offset voltage should be set to the low-reference
voltage of the ADC.
Document Number: 38-05707 Rev. *C
Digital Controls
Power and Ground
VDD_RESETL
VDD_RESETR
VDD_ARRAY
VDD
GND
Gain
Output Signal Range
Bandwidth
(40 pF Load)
Output Slew Rate
(40 pF Load)
59
79
55
11
34
53
77
10
33
52
78
Table 3.
1.2 (gain setting 0)
1 V
12 MHz
(gain setting 15)
40 V/ μs
Summarizes the specifications of the amplifier.
Power supply for left reset line drivers apply 5 V DC (default) or about 4…4.5 V for dual
slope mode
Power supply for right (default) reset line drivers 5 V DC
Power supply for the pixel array 5 V DC
Power supply of image sensor core & output amplifier 5 V DC
Ground of image sensor core & output amplifier
Min.
2.7 (setting 4)
22 MHz
(gain setting 0...8)
50 V/μs
Typ
16 (setting 15)
4.5 V
33 MHz
(gain setting 0)
80 V/μs
CYII4SM1300AA
Max
Page 9 of 35
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