CYII4SM1300AA-QDC Cypress Semiconductor Corp, CYII4SM1300AA-QDC Datasheet - Page 24

• Manufacturer Part Number: CYII4SM1300AA-QDC
• Description: SENSOR IMAGE MONO CMOS 84-LCC
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYII4SM1300AA-QDC

• Package / Case: 84-LCC
• Pixel Size: 7µm² x 7µm²
• Active Pixel Array: 1286H x 1030V
• Frames Per Second: 7
• Voltage - Supply: 5V
• Operating Supply Voltage: 5 V
• Image Size: 1280 H x 1024 V
• Color Sensing: Black/White
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: IBIS4-1300-M-2; IBIS4-1300-M-2

On-Chip Generated Electrical Dark References
The sensor outputs a electrical dark reference level after the 2nd
falling edge on the clock (after sync).
At the end of the row readout, after EOS_X becomes low, the
sensor outputs the electrical dark reference voltage also, and it
remains present on the on the readout bus until SIN goes high.
Note that if the X-register is reset before the EOS is reached, the
dark reference is not put on the bus. Use the dark reference of
the beginning of the line instead.
If the end of a row is reached, the sensor outputs an end-of-scan
(EOS) pulse during one pulse period. And the electrical black
reference level appears at the output for all successive pulses.
So, the same 10 MHz clock can drive CLK_X and CLK_ADC.
Document Number: 38-05707 Rev. *C
Clock
Output
Sync
DCREF on bus
n-1
Figure 20. Timing of X Shift Register and Pixels Readout
Min 25 ns
n
Tp,adc
nil
Figure 21. Pixel Timing
dark
0
Dummy pixels
Pixel Readout
The same continuous 10 MHz clock drives CLK_ADC and
CLK_X. On the falling edge of CLK_X, a new pixel is selected
and propagates to the output amplifier. At the same time, the
ADC input is frozen by the falling edge on CLK_ADC. The digital
output has a delay of one pixel compared to the analog signal.
The digital output becomes valid between 25 to 50 ns after the
falling edge on CLK_ADC.
Min 100 ns.
1
2
0
3
1
4
CYII4SM1300AA
Page 24 of 35
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