CYIL2SC1300AA-GZDC Cypress Semiconductor Corp, CYIL2SC1300AA-GZDC Datasheet - Page 34

• Manufacturer Part Number: CYIL2SC1300AA-GZDC
• Description: IMAGE SENSOR CMOS LUPA-1300-2
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYIL2SC1300AA-GZDC

• Pixel Size: 14µm x 14µm
• Active Pixel Array: 1280H x 1024V
• Frames Per Second: 500
• Voltage - Supply: 2.5V, 3.3V
• Package / Case: 168-PGA
• Package: 168CuPGA
• Image Size: 1280x1024 Pixels
• Color Sensing: Color
• Operating Temperature: 0 to 70 °C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Table 18. Pin List (continued)
Document Number: 001-24599 Rev. *C
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
nr
vddadc
vddlvds
clkinp
clkinn
syncp
syncn
gnddig
vdddig
cap_vrefm
cap_vrefp
gndadc
vddadc
gnddig
gndbuf
vddbuf
gndana
vddana
vpix
gndpix
vsamp
gndadc
vdddig
nbias_colload
test_ena
int_time1
int_time2
int_time3
monitor1
monitor2
monitor3
cap_vrefadc
vpix
cap_vrefcm
reset_n
scan_en
scan_clk
scan_clk_en
gndpix
gnddig
vdddig
vpix
Pin Name
Supply
Supply
Supply
Supply
Analog
Analog
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Analog
Analog
Supply
Analog
Supply
Supply
Supply
Supply
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
LVDS
LVDS
LVDS
LVDS
Type
Direction
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
digital power supply
integration pin dual slope
digital ground
ADC power
LVDS power
LVDS input clock 315 MHz p-node
LVDS input clock 315 MHz n-node
LVDS sync and output
LVDS sync and output
digital ground
lower limit ADC range decoupling
higher limit ADC range decoupling
ADC ground
ADC power supply
digital ground
column buffers ground
column buffers supply
column buffers ground
column buffers supply
pixel core supply
pixel core ground
image core select and sample supply
ADC ground
digital power supply
column bias decouple
scan pin for sequencer
integration pin first slope
integration pin triple slope
output pin for integration timing, high during integration
output pin for dual slope integration timing, high during
integration
output pin for triple slope integration timing, high during
integration
ADC black reference decoupling
pixel core supply
ADC common mode decoupling
chip reset (active low)
DFT scan enable
DFT clock
DFT clock enable
pixel core ground
digital power supply
pixel core supply
Description
CYIL2SM1300AA
Page 34 of 41
T17
U18
V19
W19
V20
W20
W24
V24
W22
V22
U20
T20
U22
W23
V23
U23
T23
T22
U21
T21
U24
T24
A24
C24
C23
B23
A23
C22
B22
A22
C21
B21
A21
C20
B20
A20
C19
B19
A19
C18
B18
Position
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