CYIL2SC1300AA-GZDC Cypress Semiconductor Corp, CYIL2SC1300AA-GZDC Datasheet - Page 8

• Manufacturer Part Number: CYIL2SC1300AA-GZDC
• Description: IMAGE SENSOR CMOS LUPA-1300-2
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYIL2SC1300AA-GZDC

• Pixel Size: 14µm x 14µm
• Active Pixel Array: 1280H x 1024V
• Frames Per Second: 500
• Voltage - Supply: 2.5V, 3.3V
• Package / Case: 168-PGA
• Package: 168CuPGA
• Image Size: 1280x1024 Pixels
• Color Sensing: Color
• Operating Temperature: 0 to 70 °C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

The 6T Pixel
To obtain the global shutter feature combined with a high
sensitivity and good parasitic light sensitivity (PLS), implement
the pixel architecture shown in
is designed in a 14 µm x 14 µm pixel pitch. The pixel is designed
to meet the specifications listed in
2. This architecture also enables pipelined or triggered mode, as
shown in
Figure 6. 6T Pixel Architecture
Frame Rate and Windowing
Frame Rate
The frame rate depends on the input clock, the frame overhead
time (FOT), and the row overhead time (ROT). The frame period
is calculated by:
Frame period = FOT+Nr. Lines * (ROT + Nr. Pixels * clock period)
Table 7. Frame Rate Parameters
Example
Readout of the full resolution at nominal speed (756 MHz pixel
rate = 1.32 ns)
Frame period = 5 µs + (1025 * (206 ns+1.32 ns*1296) = 1.97 ms
=> 507 fps
The real speed of the LUPA1300-2 is reduced to 500 fps,
because overhead pixels are read out for black level calibration
and other on board features.
Document Number: 001-24599 Rev. *C
FOT
ROT
Nr. Lines
Nr. Pixels
Clock Period 1/63 MHz = 15.9 ns Every channel works at
Reset
Parameter
Figure
Vpix
Frame Overhead
Time
Row Overhead
Time
Number of lines
read out each
frame
Number of pixels
read out each line
6.
Comment
Sample
Vmem
Figure
Table 1
Programmable: Default
315 MHz granularity clock
cycles (5 µs at 630 MHz)
Programmable: Default 13
granularity clock cycles
(206 ns at 630 MHz)
63 MHz
result in 756 MHz data rate
6. This pixel architecture
Select
Clarification
and
12 channels
Table 2
on page
Windowing
Windowing is easily achieved by SPI. The starting point of the x
and y address and the window size can be uploaded. The
minimum step size in the x-direction is 24 pixels (choose only
multiples of 24 as start or stop addresses). The minimum step
size in the y-direction is one line (every line can be addressed)
in normal mode, and two lines in sub sampling mode.
The section
registers to achieve the desired ROI.
Table 8. Typical Frame Rates for 630 MHz Clock
Analog to Digital Converter
The sensor has 24 10-bit pipelined ADCs on board. The ADCs
nominally operate at 31.5 Msamples/s.
Table 9. ADC Parameters
Programmable Gain Amplifiers
The PGAs amplify the signal before sending it to the ADCs.
The amplification inside the PGA is controlled by one SPI setting:
afemode [5:3].
Six gain steps can be selected by the afemode<5:3> register.
Table 10
PGA is done by the default afemode<5:3> setting.
Table 10. Gain Settings
Data rate
Quantization
DNL
INL
Resolution (X*Y)
afemode<5:3>
1296x1025
Parameter
640 x 512
256 x 256
Image
000
001
010
100
101
011
lists the six gain settings. The unity gain selection of the
Sequencer
31.5 Msamples/s
10 bit
Typ. < 1 DN
Typ. < 1 DN
Frame Rate
1842
6933
(fps)
507
on page 10 discusses the use of
Specification
Gain
2.25
1.5
1
2
3
4
Out Time (µs)
Frame Read
CYIL2SM1300AA
1970
550
146
Page 8 of 41
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