CYIL2SC1300AA-GZDC Cypress Semiconductor Corp, CYIL2SC1300AA-GZDC Datasheet - Page 9

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CYIL2SC1300AA-GZDC

Manufacturer Part Number
CYIL2SC1300AA-GZDC
Description
IMAGE SENSOR CMOS LUPA-1300-2
Manufacturer
Cypress Semiconductor Corp
Type
CMOS Imagingr
Datasheet

Specifications of CYIL2SC1300AA-GZDC

Pixel Size
14µm x 14µm
Active Pixel Array
1280H x 1024V
Frames Per Second
500
Voltage - Supply
2.5V, 3.3V
Package / Case
168-PGA
Package
168CuPGA
Image Size
1280x1024 Pixels
Color Sensing
Color
Operating Temperature
0 to 70 °C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Operation and Signaling
Digital Signals
Depending on the operation mode (Master or Slave), the pixel array of the image sensor requires different digital control signals. The
function of each signal is listed in this table.
Table 11. Overview of Digital Signals
Synchronous Shutter
In a synchronous (snapshot or global) shutter, light integration occurs on all pixels in parallel, although subsequent readout is
sequential.
period of time. The whole pixel core is reset simultaneously, and after the integration time, all pixel values are sampled together on
the storage node inside each pixel. The pixel core is read out line by line after integration. Note that the integration and readout cycle
can occur in parallel or in sequential mode (pipelined or triggered). Refer to the section
Document Number: 001-24599 Rev. *C
MONITOR_1
MONITOR_2
MONITOR_3
INT_TIME_3
INT_TIME_2
INT_TIME_1
RESET_N
CLK
SPI_CS
SPI_CLK
SPI_IN
SPI_OUT
Signal Name
Figure 7
shows the integration and readout sequence for the synchronous shutter. All pixels are light sensitive at the same
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Output
Line number
I/O
Integration Time
Output pin for integration timing, high during integration
Output pin for dual slope integration timing, high during integration
Output pin for triple slope integration timing, high during integration
Integration pin triple slope
Integration pin dual slope
Integration pin first slope
Sequencer reset, active LOW
System clock (630 MHz)
SPI chip select
Clock of the SPI
Data line of the SPI, serial input
Data line of the SPI, serial output
Figure 7. Synchronous Shutter Operation
Comments
Burst Readout
ti
Image Sensor Timing and Readout
Time axis
CYIL2SM1300AA
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