CYIL2SC1300AA-GZDC Cypress Semiconductor Corp, CYIL2SC1300AA-GZDC Datasheet - Page 7

• Manufacturer Part Number: CYIL2SC1300AA-GZDC
• Description: IMAGE SENSOR CMOS LUPA-1300-2
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYIL2SC1300AA-GZDC

• Pixel Size: 14µm x 14µm
• Active Pixel Array: 1280H x 1024V
• Frames Per Second: 500
• Voltage - Supply: 2.5V, 3.3V
• Package / Case: 168-PGA
• Package: 168CuPGA
• Image Size: 1280x1024 Pixels
• Color Sensing: Color
• Operating Temperature: 0 to 70 °C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Table 5. Power Dissipation
These specifications apply for V
Table 6. AC Electrical Characteristics
The following specifications apply for VDD = 2.5V, Clock = 315 MHz, 500 fps.
Sensor Architecture
The floor plan of the architecture is shown in
transmitters and receivers. Separate modules for the SPI, clock division, and sequencer are also integrated. The image sensor of
1280 x 1024 pixels is read out in progressive scan.
This architecture enables programmable addressing in the x-direction in steps of 24 pixels, and in the y-direction in steps of one pixel.
The starting point of the address can be uploaded by the serial parallel interface (SPI).
The AFE prepares the signal for the digital data block when the data is multiplexed and prepared for the LVDS interface.
Document Number: 001-24599 Rev. *C
P
Power
F
DC
fps
DOWN
CLK
CLK
Symbol
Symbol
Power down
Average Power Dissipation
Input Clock Frequency
Clock Duty Cycle
Frame rate
[3]
DD
24x 10-bit digital channels
Parameter
Parameter
12x 10-bit digital channels
= 2.5V, Clock = 315 MHz, 500 fps
24 analog channels
[3]
Figure
Figure 5. Floor Plan of the Sensor
12x LVDS outputs at 630 Msps
5. The sensor consists of a pixel array, analog front end, data block, and LVDS
Analog front end
LVDS TX and RX
1280 x 1024
Image core
Local register
Data block
no clock running
lux = 0
fps = 500
At maximum clock
Maximum clock speed
31.5 Msps
31.5 Msps
63 Msps
Condition
Condition
Clk X & Clk Y
31.5 MHz
63 MHz
315 MHz
Sequencer
Divider
Logic
Clock
SPI
&
Clk out
Clk in
Typ
50
1350
Typ
400
CYIL2SM1300AA
Max
500
315
Units
Units
MHz
mW
mW
fps
%
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